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CMX910 ais baseband processor ? 2009 cml microsystems plc d/910/6 march 2009 provisional issue features: ? half-duplex gm(f)sk, fsk and dsc capabilities ? i and q radio interface ? slot/sample counter with utc timing interface ? low-power (3.0 to 3.6v) operation ? optimum co-channel and adjacent-channel performance ? low profile, 64-lead lqfp (l9) and leadless vqfn (q1) packages ? flexible signal channels ? two simultaneous rx ? one tx ? optional fsk interface ? auxiliary adc and dac functions ? 5 x (10-bit) dacs ? 5-input mux (10-bit) adc ? ais data formatted and raw data modes applications: ? supports carrier-sensing channel access (cstdma) operation ? automatic identification system (ais) for marine safety ? rf device-enable facilities ? class a or b ais transponders ? c-bus serial interface with expansion port ? ais rx-only modules hdlc/ nrzi decoder message buffers gmsk/ fsk decoder hdlc/ nrzi encoder message buffer gmsk/ fsk encoder hdlc/ nrzi decoder message buffers gmsk/ fsk decoder aux adc aux dacs device enable port fsk retiming (external) reset and power control slot and sample timer interrupt generator c-bus interface c-bus expansion port CMX910 rf rx1: i/q down- converter tx: i/q up- converter rx2: i/q down- converter ? adcs ? adcs ? dacs radio host c gnss engine other c-bus devices optional fsk demod. (fx604) tcxo 1. brief description a highly integrated baseband signalling processor ic, t he CMX910 fulfils the requi rements of the class a and class b marine automatic identif ication system (ais) transponder ma rket. the CMX910 is half duplex in operation, comprising two parallel i+q rx paths and one tx path. these are configurable for ais or dsc operation. the device performs channel filt ering and signal modulation/demodulation with associated ais functions, such as training s equence detection, nrzi conversion and hdlc processing (flags, bit stuffing/de-stuffing, crc generate/check). an external 1200bps fsk demodulator interface provides a third parallel decode path for dsc, as r equired by the class a market. integrated rx/tx data buffers and a flexible slot/sample timer are also pr ovided, all of which great ly reduce the processing requirements of the host c. provision of a c-bus expansion port, an rf device enable port and a number of auxiliary adcs and dacs fu rther simplifies the system hardw are design, reducing the overall equipment cost and size.
ais baseband processor CMX910 ? 2009 cml microsystems plc 2 d/910/6 contents section page 1. brief d escription ................................................................................................. 1 2. block diagram ..................................................................................................... 4 3. signa l list ............................................................................................................ 5 4. external components ......................................................................................... 7 5. general descrip tion ............................................................................................ 8 5.1 ov erview of CMX910 oper ation............................................................ 8 5.2 c-bus interf ace ...................................................................................... 9 5.3 reset and po wer cont rol .................................................................... 12 5.3.1 reset n pin ............................................................................. 12 5.3.2 general reset co mmand ....................................................... 12 5.3.3 clock control ........................................................................... 12 5.4 slot and sa mple timer ........................................................................ 13 5.4.1 manual nudge .......................................................................... 16 5.4.2 auto nudge .............................................................................. 17 5.4.3 sleep mode .............................................................................. 17 5.4.4 selecting the nudge_trigge r value ...................................... 18 5.5 transmit operation .............................................................................. 19 5.5.1 transmitte r regist ers ............................................................. 19 5.5.2 ais raw m ode transmit ......................................................... 24 5.5.3 ais burst mode transmit ....................................................... 25 5.5.4 dsc transmit .......................................................................... 27 5.5.5 transmitter timing c ontrol .................................................... 29 5.6 receiv e operation................................................................................ 32 5.6.1 receiv er registers.................................................................. 33 5.6.2 ais raw mode receive........................................................... 37 5.6.3 ais burst mode r eceive......................................................... 38 5.6.4 dsc receive (main ch annel) ................................................. 39 5.6.5 dsc receive (ext ernal fsk interf ace).................................. 39 5.7 auxiliary a-to -d conv erter .................................................................. 40 5.8 auxiliary d-to -a conv erters................................................................ 42 5.9 interrupt genera tor .............................................................................. 46 5.10 dev ice en able port............................................................................... 48 5.11 c-bus expa nsion port ........................................................................ 49 5.12 special command inte rface................................................................ 50 6. supplementary information ............................................................................. 52 6.1 glossary of terms................................................................................ 52 7. performance specificat ion ............................................................................... 54 7.1 electrical performa nce ........................................................................ 54 7.1.1 absolute maximum ratings ................................................... 54 7.1.2 operat ing limits ...................................................................... 54 7.1.3 operating characteristics ...................................................... 55 7.2 packag ing ............................................................................................. 60
ais baseband processor CMX910 ? 2009 cml microsystems plc 3 d/910/6 table page table 1 summary of c-bus r egisters ............................................................................ 11 table 2 example tx event sequenc e setup ................................................................... 31 figure page figure 1 CMX910 block di agram ...................................................................................... 4 figure 2 recommended external co mponents................................................................. 7 figure 3 basic c- bus trans actions .................................................................................. 9 figure 4 c-bus data-streaming o peratio n .................................................................... 10 figure 5 slot and samp le timer circui t ........................................................................... 13 figure 6 tr ansmit channel .............................................................................................. 19 figure 7 tx (ais raw mode) state transit ions .................................................................. 25 figure 8 tx (ais burst mode) state transit ions ................................................................ 27 figure 9 tx (dsc m ode) state tr ansiti ons........................................................................ 28 figure 10 typical ais trans mission ................................................................................ 29 figure 11 re ceive channel ............................................................................................. 32 figure 12 aux iliary adc................................................................................................... 40 figure 13 aux iliary dacs ................................................................................................. 42 figure 14 ramd ac values ............................................................................................. 45 figure 15 i/q filter res ponse in 25khz operat ion. ........................................................... 59 figure 16 c- bus timing .................................................................................................. 59 figure 17 q1 mechanical outline: order as part no. CMX910q1 .................................. 60 figure 18 l9 mechanical outline: order as part no. CMX910l9 .................................... 61 history version changes date 1 - 5 earlier versions, for which a hi story file is not maintained. 20/11/0 8 6 ? corrected description of the operation of the auto nudge acquire sequence in section 5.4.2. 26/03/0 9 it is always recommended that you check for t he latest product datasheet version from the datasheets page of the cml w ebsite: [www.cmlmicro.com].
ais baseband processor CMX910 ? 2009 cml microsystems plc 4 d/910/6 2. block diagram ? adc ? adc i q irx1p irx1n qrx1n qrx1p d dt level tracking gmsk slicer hdlc/ nrzi decoder message buffers rx1 fifo ? dac ? dac i q itxp itxn qtxn qtxp cos hdlc/ nrzi encoder message buffer tx fifo sin dt fsk mod. fsk demod. vbias bias gen. irx2p irx2n qrx2n qrx2p avss ? adc ? adc i q d dt level tracking gmsk slicer hdlc/ nrzi decoder message buffers rx2 fifo fsk demod. rx channel 1 rx channel 2 tx channel avdd analogue 2v5 regulator avss iovdd enab0 enab1 enab2 enab3 enab4 enab5 device enable port fsk rx (ext.) dvss fsk_mute fsk_det fsk_rxd reset and power control refclk slot and sample timer utc1pps slotclkn resetn fsk retiming fsk fifo exp0n exp1n exp2n exp3n exp4n exp5n c-bus expansion port dvss csxn csn cdata sclk rdata c-bus interface dvdd iovdd interrupt generator irqn digital 2 v 5 regulator special command interface auxadc2p auxadc2n a uxadc2fb auxadc1p auxadc1n a uxadc1fb auxadc0p auxadc0n a uxadc0fb auxadc3 auxadc4 avdd aux adc 10-bit dac aux dacs auxdac4 10-bit dac auxdac3 10-bit dac auxdac2 10-bit dac 10-bit dac auxdac1 auxdac 0 dac ram 10-bit adc s/h mux avss figure 1 CMX910 block diagram
ais baseband processor CMX910 ? 2009 cml microsystems plc 5 d/910/6 3. signal list package q1 or l9 signal description pin no. name type 1 av ss power analogue negative supply rail (ground) 2 irx1p i/p receive ?i? channel 1, positive input 3 irx1n i/p receive ?i? channel 1, negative input 4 qrx1p i/p receive ?q? channel 1, positive input 5 qrx1n i/p receive ?q? channel 1, negative input 6 vbias o/p a bias line for the internal circuitry, held at ? av dd . this pin must be decoupled to av ss by a capacitor mount ed close to the device pins 7 itxp o/p transmit ?i? channel, positive output 8 itxn o/p transmit ?i? channel, negative output 9 qtxp o/p transmit ?q? channel, positive output 10 qtxn o/p transmit ?q? channel, negative output 11 av ss power analogue negative supply rail (ground) 12 irx2p i/p receive ?i? channel 2, positive input 13 irx2n i/p receive ?i? channel 2, negative input 14 qrx2p i/p receive ?q? channel 2, positive input 15 qrx2n i/p receive ?q? channel 2, negative input 16 av dd power analogue positive supply rail. decouple to av ss 17 iov dd power digital i/o positive supply rail. decouple to dv ss 18 enab0 o/p enable output 0 19 enab1 o/p enable output 1 20 enab2 o/p enable output 2 21 enab3 o/p enable output 3 22 enab4 o/p enable output 4 23 enab5 o/p enable output 5 24 dv ss power digital negative supply rail (ground) 25 fsk_mute i/p fsk rf squelch indicator 26 fsk_det i/p fsk baseband energy detect indicator 27 fsk_rxd i/p raw fsk demodulator input data 28 refclk i/p master input clock (multiple of 2.4mhz) 29 resetn i/p active low chip reset 30 utc1pps i/p 1hz utc sync pulse, typically from gnss receiver 31 slotclkn o/p slot clock output (active low), pulse s at the start of each ais slot. configurable as a ?wire-orable? output, requiring an external pullup resistor, or as an active pullup/pulldown. 32 irqn o/p a ?wire-orable? output for connection to the host c's interrupt request input. this output has a low impedance pull down to dv ss when active and is high impedance when inactive. an external pullup resistor is required.
ais baseband processor CMX910 ? 2009 cml microsystems plc 6 d/910/6 package q1 or l9 signal description pin no. name type 33 exp0n o/p chip select expansion output 0 (active low) 34 exp1n o/p chip select expansion output 1 (active low) 35 exp2n o/p chip select expansion output 2 (active low) 36 exp3n o/p chip select expansion output 3 (active low) 37 exp4n o/p chip select expansion output 4 (active low) 38 exp5n o/p chip select expansion output 5 (active low) 39 dv ss power digital negative supply rail (ground) 40 csxn i/p chip select expansion input (active low) 41 csn i/p chip select input (active low), used to enable a c-bus data read or write operation on the chip. 42 cdata i/p the c-bus serial data input from the c. 43 sclk i/p the c-bus serial clock input from the c. 44 rdata t/s a 3-state c-bus serial data output to the c. this output is high impedance when not sending data to the c. 45 dv dd power digital core positive supply rail. decouple to dv ss 46 iov dd power digital i/o positive supply rail. decouple to dv ss 47 auxdac0 o/p auxiliary d-to-a converter output 0 (with ramp) 48 auxdac1 o/p auxiliary d-to-a converter output 1 49 auxdac2 o/p auxiliary d-to-a converter output 2 50 auxdac3 o/p auxiliary d-to-a converter output 3 51 auxdac4 o/p auxiliary d-to-a converter output 4 52 av ss power analogue negative supply rail (ground) 53 auxadc0fb o/p auxiliary a-to-d converter 0, amplifier feedback 54 auxadc0n i/p auxiliary a-to-d converter 0, amplifier -ve input 55 auxadc0p i/p auxiliary a-to-d converter 0, amplifier +ve input 56 auxadc1fb o/p auxiliary a-to-d converter 1, amplifier feedback 57 auxadc1n i/p auxiliary a-to-d converter 1, amplifier -ve input 58 auxadc1p i/p auxiliary a-to-d converter 1, amplifier +ve input 59 auxadc2fb o/p auxiliary a-to-d converter 2, amplifier feedback 60 auxadc2n i/p auxiliary a-to-d converter 2, amplifier -ve input 61 auxadc2p i/p auxiliary a-to-d converter 2, amplifier +ve input 62 auxadc3 i/p auxiliary a-to-d converter input 3 63 auxadc4 i/p auxiliary a-to-d converter input 4 64 av dd power analogue positive supply rail. decouple to av ss e xposed m etal p ad dv ss power this pad (which is only present on the q1 package) must be connected to digital ground (0v). notes: i/p = input o/p = output bi = bidirectional t/s = 3-state output nc = no connection
ais baseband processor CMX910 ? 2009 cml microsystems plc 7 d/910/6 4. external components irx1p irx1n qrx1n qrx1p itxp itxn qtxn qtxp vbias irx2p irx2n qrx2n qrx2p avss avdd avss iovdd enab0 enab1 enab2 enab3 enab4 enab5 dvss fsk_mute fsk_det fsk_rxd refclk utc1pps slotclkn resetn exp0n exp1n exp2n exp3n exp4n exp5n dvss csxn csn cdata sclk rdata dvdd iovdd irqn auxadc2p auxadc2n auxadc2fb auxadc1p auxadc1n auxadc1fb auxadc0p auxadc0n auxadc0fb auxadc3 auxadc4 avdd auxdac4 auxdac3 auxdac2 auxdac1 auxdac0 avss avss r1 c1 avss r2 c2 avss r3 c3 avss r4 c4 avss r5 c5 avss r6 c6 avss r7 c7 avss r8 c8 avss c19 avss c14 r12 avss c12 r11 avss c11 r10 avss c10 r9 avss c9 avss c13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 iovdd 18 19 20 2221 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dvss r13 dvdd dvdd dvss iovdd CMX910 c20 c16 c18 analogue ground plane digital ground plane c17 avss c15 a vss avss avss dvss dvss dvss dvss avss wirelink connect qfn ground slug to digital ground (dv ) ss figure 2 recommended external components c1-c8 1nf c14-c18 10nf r1-r8 1k c9-c12 1nf c19 10f r9-r12 1k c13 1f c20 22f r13-r14 10k a regulated 3.3v supply must be connected to the CMX910?s iov dd pins in order to supply the digital i/o pad circuitry. this 3.3v supply is also used by two on-chip 2.5v regulators which are used to generate the separate av dd and dv dd supplies (used by the CMX910?s on-chip analogue and digital circuitry), the only external components needed are the decoupling capacitors. the av dd and dv dd supplies are not intended to provide current to any external circuits, but may be buffered if required for use as a reference. to achieve good noise performance, av dd /dv dd and vbias decoupling and protection of the receive path from extraneous in-band signals are very important. it is recommended that the printed circuit board is laid out with separate analogue and digital gr ound planes in the CMX910 area to provide a low impedance connection between av ss and the av dd /vbias decoupling capacitors, and between dv ss and the dv dd decoupling capacitors.
ais baseband processor CMX910 ? 2009 cml microsystems plc 8 d/910/6 5. general description 5.1 overview of CMX910 operation the CMX910 ic has two main receiver circuits t hat support simultaneous reception of two ais channels, or one ais and one dsc channel. when the two main rece ive channels are configured for ais reception, a supplementary dsc-only receiver can be supported by using a separate external fsk demodulator (such as the fx604) interfaced to the CMX910. data bits received on this fsk interface get packed into bytes and passed through to the host c. transmission on a single channel (ais or dsc) is supported, during which all reception ceases. the main re ceive and transmit channels use differential i + q signalling, and digital filtering and signal processi ng techniques are used to obtain a high level of performance. the CMX910 also supports the proposed carrier-sens ing channel access scheme (cstdma) for the ais class b standard. overall timing synchronisation centres around two count ers, one counting the number of samples per slot, the other the number of slots in a minute. these allow the c to retrieve slot and sample timing information for any received message as well as specifying transmit timing accurately. counters can be synchronised to an external 1 pulse per second utc re ference signal or allowed to run free, in which case they must be kept in alignment by the c. the CMX910 offers full frame-formatting (hdlc-type) support for ais receive and transmit, including nrzi coding, bit stuffing and de-stuffing, training sequence, start/stop flag insertion and deletion, and crc generation and checking. a raw mode is also prov ided allowing greater flexibility. dsc transmission and reception is only supported in t he equivalent of the ais raw mode. the transmit channel and three receive channels interf ace to the c through individual 32-deep, byte wide first-in first-out data buffers. these alleviat e latency problems and allow higher data rates between the c and the CMX910. to allow system perfo rmance to be further enhanced, the CMX910 can be configured to cause an interrupt if the transmit fifo fill level drops below a user-defined threshold or any of the receive fifos? fill levels exceed a user-defined threshold. the CMX910 also assists with power saving and control of critical external rf circuits by providing a flexible device enable port. further monitoring and control functions can be implemented using the integrated auxiliary adc and dac circuits. communication between the CMX910 and the host c is done through cml?s standard c-bus interface and interrupt pin. the c-bus interface is spi compatible, and can be driven by an spi master controller. a c-bus expansion port is also provided which allows the connection of up to six further c-bus or spi compatible devices to the c. note: to further enhance the CMX910, its special co mmand interface (see section 5.12) can be used to reconfigure the CMX910?s functionality to fu lly implement and improve its cs-tdma reception capability and slot-clock synchronisation.
ais baseband processor CMX910 ? 2009 cml microsystems plc 9 d/910/6 5.2 c-bus interface this block provides for the transfer of data and c ontrol or status inform ation between the CMX910?s internal registers and the host c over the c-bus serial bus. each transaction consists of a single register address byte sent from the c which may be followed by a data word sent from the c to be written into one of the CMX910?s write only registers, or a data word read out from one of the CMX910?s read only registers; all c-bus data words are a multiple of 8 bits wide, the width depending on the source or destination register. note that certain c-bus transactions require only an address byte to be sent from the c, no data transfer being required. the operation of the c-bus is illustrated in figure 3. data sent from the c on the cdata (command data) line is clocked into the CMX910 on the rising edge of the sclk input. data sent from the CMX910 to the c on the rdata (reply data) line is valid when sclk is high. the csn line must be held low duri ng a data transfer and kept high between transfers. the c-bus interface is compatible with most comm on c serial interfaces and may also be easily implemented with general purpose c i/o pins controlled by a simple software routine. figure 16 gives detailed c-bus timing requirements. c-bus single byte command (no data) note: the sclk line may be high or low at the start and end of each transaction. see figure 16 . = level not important c-bus n-bit register write csn sclk cdata 7 6 5 4 3 2 1 0 n-1 n-2 n-3 2 1 0 msb address lsb msb write data lsb rdata hi-z c-bus n-bit register read csn sclk cdata 7 6 5 4 3 2 1 0 msb address lsb rdata hi-z n-1 n-2 n-3 2 1 0 msb read data lsb figure 3 basic c-bus transactions csn sclk cdata 7 6 5 4 3 2 1 0 msb address lsb rdata hi-z
ais baseband processor CMX910 ? 2009 cml microsystems plc 10 d/910/6 to increase the data bandwidth between the c and t he CMX910, certain of the c-bus read and write registers are capable of data-streami ng operation. this allows a single address byte to be followed by the transfer of multiple read or write data words, all within the same c-bus transacti on. this can significantly increase the transfer rate of large data blocks, as shown in figure 4. example of c-bus data-streaming (8-bit write register) csn sclk cdata 7 6 5 4 3 21 0 7 6 5 4321076543210 7 6 5 4 3 2 10 address first byte second byte ? last byte rdata hi-z example of c-bus data-streaming (8-bit read register) csn sclk cdata 7 6 5 4 3 2 1 0 address rdata hi-z 7 6 5 4321076543210 7 6 5 4 3 2 10 first byte second byte ? last byte figure 4 c-bus data-streaming operation a summary of the CMX910?s c-bus addresses and registers are shown in table 1. note: the CMX910?s internal clock must be running before any c-bus a ccess is attempted, with the exception of the general_reset command and the clock_ control and cbus_expand registers.
ais baseband processor CMX910 ? 2009 cml microsystems plc 11 d/910/6 table 1 summary of c-bus registers c-bus register name addr r/w/ cmd size c-bus register name addr r/w/ cmd size reset and power control fsk interface general_reset $01 cmd - fsk_fifo (ds) $50 r 8 clock_control $02 w 8 fsk_fifo_threshold $51 w 8 slot and sample timer fsk_status $52 r 16 slot_sample_control $10 w 8 fsk_control $53 w 8 slot_sample_count $11 r 32 auxiliary adc sleep_sample $12 w 16 adc0 $60 r 16 wakeup_sample $13 w 16 adc1 $61 r 16 slot_sample_utc1pps $14 r 32 adc2 $62 r 16 slot_nudge $15 w 16 adc3 $63 r 16 sample_nudge $16 w 16 adc4 $64 r 16 nudge_trigger $17 w 16 adc_control1 $65 w 8 max_auto_nudge $18 w 16 adc_control2 $66 w 8 transmit channel adc_status $67 r 8 tx_fifo (ds) $20 w 8 adc_convert $68 cmd - tx_fifo_threshold $21 w 8 auxiliary dacs tx_status $22 r 16 dac0 $70 w 16 tx_slot $23 w 16 dac1 $71 w 16 tx_bits $24 w 16 dac2 $72 w 16 tx_control $25 w 16 dac2 $73 w 16 cstdma_threshold $26 w 16 dac4 $74 w 16 receive channel 1 dac_control $75 w 8 rx1_fifo (ds) $30 r 8 dac0_rampup $76 cmd - rx1_fifo_threshold $31 w 8 dac0_rampdown $77 cmd - rx1_status $32 r 16 dac0_timestep $78 w 8 rx1_slot $33 r 16 dac_ram_load (ds) $79 w 16 rx1_sample $34 r 16 interrupts rx1_bytes $35 r 16 interrupt $80 r 16 rx1_control $36 w 8 interrupt_enable $81 w 16 rx1_freqerr $37 r 16 device enable port rx1_rssi $38 r 16 enab $90 w 8 receive channel 2 enab_mask $91 w 8 rx2_fifo (ds) $40 r 8 enab_invert $92 w 8 rx2_fifo_threshold $41 w 8 c-bus expansion port rx2_status $42 r 16 cbus_expand $a0 w 8 rx2_slot $43 r 16 special command interface rx2_sample $44 r 16 spc_in0 $b0 w 16 rx2_bytes $45 r 16 spc_in1 $b1 w 16 rx2_control $46 w 8 spc_out0 $b2 r 16 rx2_freqerr $47 r 16 special_command $b4 w 8 rx2_rssi $48 r 16 (ds) - these registers are capabl e of data-streaming transactions. note: c-bus addresses $f0 to $fe are allocated for produc tion testing and should not be accessed in normal operation.
ais baseband processor CMX910 ? 2009 cml microsystems plc 12 d/910/6 5.3 reset and power control 5.3.1 resetn pin the CMX910 is reset by taking resetn low, which c auses all internal clocks and bias currents to be disabled and all c-bus registers to be reset. to bri ng the CMX910 out of this quiescent state after resetn is pulled high, a stable clock signal must firs t be applied to the refclk input pin (any multiple of 2.4mhz up to a maximum of 24mhz), then the cl ock_control register must be programmed with the frequency of the applied refclk. a period of 10ms must then elapse to allow the CMX910 to initialise, after which time the device is ready for operati on. during operation the main rx and tx channel analogue circuits and auxiliary adc and dac circuits will be powered up as required, depending on how the host c sets various c-bus contro l and configuration registers. 5.3.2 general_reset command general_reset command (no data) c-bus address $01 this command disables all internal bias currents and resets all c-bus registers except for cbus_expand and clock_control. this means that if the CMX910?s internal clocks ar e running, they will remain running when general_reset is applied. after a general_reset command, a period of 10ms must elapse to allow the CMX910 to initialise before any further c-bus operations are attempted. 5.3.3 clock control the CMX910 can be put back into a low power state at any time by writing $00 to the clock_control register. this will disable all internal clocks and bi as currents and reset all internal c-bus registers except for cbus_expand. to subsequently bri ng the CMX910 out of this low power state requires the same sequence of operations as if a resetn pulse had been applied. clock_control register: 8-bit write only. c-bus address $02 all bits cleared to 0 when resetn pin asserted. regi ster contents are not affe cted by a general_reset command. this register can be written while the CMX910?s internal clocks are disabled. bit: 7 6 5 4 3 2 1 0 reserved, set to 0000 refclk mult. factor clock_control register b3-0: refclk multiplication factor b3 b2 b1 b0 0 0 0 0 internal clocks disabled, device held in low power mode 0 0 0 1 refclk = 2.4mhz 0 0 1 0 refclk = 4.8mhz 0 0 1 1 refclk = 7.2mhz 0 1 0 0 refclk = 9.6mhz 0 1 0 1 refclk = 12.0mhz 0 1 1 0 refclk = 14.4mhz 0 1 1 1 refclk = 16.8mhz 1 0 0 0 refclk = 19.2mhz 1 0 0 1 refclk = 21.6mhz 1 0 1 0 refclk = 24.0mhz codes 1011 2 to 1111 2 are reserved, do not use
ais baseband processor CMX910 ? 2009 cml microsystems plc 13 d/910/6 5.4 slot and sample timer the slot and sample timer circuit contains tw o counters that are used to control and sequence operations in the three main channels (rx1, rx2, tx). slot_sample_count slot_sample_utc1pps sample counter (11 bit) a+b slot counter (12 bit) a+b 48 khz overflow sample_nudge slot_nudge c-bus nudge max_auto_nudge slot_sample_control nudge_trigger a=b comparator wakeup_sample a=b comparator sleep_sample a=b comparator slotclk n utc1pps pin ctrl slot and sample nudge control logic load sample_count slot_count figure 5 slot and sample timer circuit the clock for the slot and sample counters is derived from the refclk input pin. the sample counter is an 11 bit counter which increments at 48khz, i.e. five times per ais data bit, and is used to time various rx and tx operations within a slot period. since there are 256 bit periods per ais slot, the sample counter increments from 0 to 1279 before rolling over to 0. the slot counter is a 12 bit counter and is used to count the slot number in an ais frame, which lasts for a minute. it is incremented at the beginning of each ais slot period, i.e. when the sample counter rolls over. there are 37? slots per second, resulting in 2250 slots per minute. therefore the sl ot counter increments from 0 to 2249 before rolling over to 0. when operating correctly, the slot counter rollover should be aligned to the star t of the utc minute. the current value of the slot and sample counters are available to the c by reading the slot_sample_count register. the CMX910 produces a pulse on its slotclkn output pin during the first sample period within each slot, this can be used as general timing reference by the c. each pulse is active low and lasts for approximately 20.83 s, and the pulses repeat at 37. 5hz. the signal appearing on the slotclkn pin can be configured to be open-drain pull-down or have active pull-up and pull-down drivers. when the CMX910 comes out of reset the slot and sample counters will be free running but not synchronised to anything. the c must synchronise them to an appropriate timing source, either utc (direct or indirect) or to an appropriate base st ation as required by recommendation itu-r m1371-1. once initial synchronisation has been established, o ccasional minor adjustments, or ?nudges?, to the sample counter must be made to keep it locked to t he chosen timing source ? this compensates for any slight drift caused by inaccuracy in the refc lk frequency. nudge values can be calculated and applied directly by the c in a software control loop (?manual nudge?, section 5.4.1). alternatively, the CMX910 can be configured into certain ?auto nudge? modes to establish initial synchronisation and subsequent
ais baseband processor CMX910 ? 2009 cml microsystems plc 14 d/910/6 tracking of the slot and sample counters with mini mal c intervention, using the utc1pps signal as a timing reference (section 5.4.2). a ?sleep control? feature is provided which can reduce power consumption significantly when the CMX910 is enabled for ais reception. this operates by automatically turning off the internal receiver circuits during inactive slots. sleep control is described in more detail in section 5.4.3. the slot and sample timer circuit is configur ed and controlled through nine c-bus registers: slot_sample_control register: 8- bit write only. c-bus address $10 register reset to $80. bit: 7 6 5 4 3 2 1 0 slot clock ctrl reserved, set to 0000 en sleep mode nudge mode slot_sample_control register b7: slotclkn pin control with b7 = 0 the slotclkn pin will be configured to have active pull-up and pull-down drivers. if b7 = 1 the pin will have an open-drain pull-down, requiring an external pull-up resistor. slot_sample_control register b2: enable sleep mode setting b2 = 1 enables ais sleep mode on receive channels rx1 and rx2. slot_sample_control register b1-0: nudge mode the nudge mode bits control how the CMX910 ac hieves and maintains synchronisation of the slot and sample counters with the utc timing reference. b1 b0 0 0 manual nudge (auto nudge disabled) 0 1 auto nudge acquire 1 0 auto nudge track 1 1 reserved, do not use slot_sample_count register: 32-bi t read only. c-bus address $11 all bits cleared to 0 on reset. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 slot count bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 sample count the slot_sample_count register holds the curr ent value of the slot and sample counters.
ais baseband processor CMX910 ? 2009 cml microsystems plc 15 d/910/6 sleep_sample register: 16-bit write only. c-bus address $12 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 00000 sleep sample value the sleep_sample register holds the sample val ue at which the CMX910?s rx1 or rx2 circuits enter sleep mode during an inactive slot. wakeup_sample register: 16-bit write only. c-bus address $13 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 00000 wakeup sample value the wakeup_sample register holds the sample val ue at which the CMX910?s rx1 or rx2 circuits leave sleep mode after an inactive slot, in time to detect a training sequence in the next slot. slot_sample_utc1pps register: 32- bit read only. c-bus address $14 all bits cleared to 0 on reset. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 slot count at last rising edge of utc1pps bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 sample count at last rising edge of utc1pps the slot_sample_utc1pps register indicates the va lue that the slot and sample counters held at the last rising edge of the utc1pps pin. slot_nudge register: 16-bit write only. c-bus address $15 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 slot nudge value (two?s complement) the slot_nudge register is written with the amount that the slot counter is to be adjusted at the next nudge trigger point. sample_nudge register: 16-bit write only. c-bus address $16 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sample nudge value (two?s complement) the sample_nudge register is written with the am ount that the sample counter is to be adjusted at the next nudge trigger point (only in m anual nudge mode, the sample_nudge register is ignored when in either of the auto nudge modes).
ais baseband processor CMX910 ? 2009 cml microsystems plc 16 d/910/6 nudge_trigger register: 16-bit write only. c-bus address $17 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 00000 sample count at which to add nudge values the nudge_trigger register holds the sample c ount at which the slot and sample counter nudge values get added. max_auto_nudge register: 16-bit write only. c-bus address $18 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 00000 maximum auto nudge value the max_auto_nudge register is used to set t he magnitude of the maximum sample counter nudge in auto nudge track mode. 5.4.1 manual nudge manual nudge mode is enabled by setting slot_sample_c ontrol b1-0 to 00 (auto nudge disabled). it is then the responsibility of the c to keep the slot and sample counters aligned to the relevant timing reference. to assist with manual nudge mode in the case where a utc time reference is available, the CMX910 copies the value of the slot_sample_count register into the slot_sample_utc1pps register on each rising edge of the utc1pps input pin, from w here it can be read by the c; the utc1pps pin should be connected to a 1hz signal whose rising edge is accurately aligned to the utc second. any error in the slot and sample counter values can t hen be easily determined. if the accurate 1hz signal is lost or not available, the same information must be derived from timing information received on the ais channels; this is made available in the rx1_slo t / rx1_sample and rx2_slot / rx2_sample registers (see section 5.6.1). note: since there are 37? slot s per second, ?even? seconds correspond to a slot boundary and ?odd? seconds correspond to the middle of a slot. in manual nudge mode, the c initially synchronises the slot and sample counters, and can subsequently make minor adjustments to the sample counter, usi ng the same mechanism in each case: the c loads the slot_nudge and sample_nudge registers with two?s-co mplement values indicating by how much the slot and sample counters should be adjusted, and t he nudge_trigger register is loaded with the exact sample time within a slot that these nudge val ues should be added to the counters ? typically, the nudge_trigger value will need to be initialised onl y once. as soon as the nudge has been done, a ?nudge_done? interrupt will be generated by t he CMX910 and the slot_nudge and sample_nudge registers will be cleared to $0000, ready for new values to be written. the slot counter usually needs adjusting only after a device reset, or if slot alignment has been lost for some reason, e.g. a gnss timing signal has been lost for some time and has just been re-acquired. if the slot counter needs adjusting, the c should writ e to the slot_nudge register first, then to the sample_nudge register. the act of writing to the sa mple_nudge register indicates to the CMX910 that both nudge values are ready, and they get applied simultaneously at the next nudge trigger point. if, however, only the sample counter needs adjusting then the c need only write to the sample_nudge register, since slot_nudge will have been previously auto-cleared. depending on the accuracy of the refclk input signal, it may be necessary to make several adjustments to the sample counter every minute. for instance, a 5ppm error in refclk will cause the sample counter to drift by 14.4 counts (nearly 3 bit periods) per minute. note that the slot counter ?wraps? properly when it is nudged forwards past 2249 or backwards past 0, but the same does not apply to the sample counter ? it can get it into an illegal state by nudging forward past 1279 or backwards past 0. avoi d this by ensuring that 0 (nudge_trigger + sample_nudge) 1279.
ais baseband processor CMX910 ? 2009 cml microsystems plc 17 d/910/6 5.4.2 auto nudge two auto nudge modes are provided which assist the c with the initial synchronisation of the slot and sample counters, and allow the CMX910 to subsequently keep the sample counter aligned without further intervention. this requires an accurate utc1pps signal to be applied to the CMX910: auto nudge acquire (slot_sample_control b1-0 = 01). this mode can be used for initial counter synchronisation after a device reset or in the case where the slot and sample counters have become grossly misaligned for some reason. auto nudge acquire should be enabled when the CMX910 has just received a utc1pps rising edge from an ?even? utc second, which means that the next utc1pps rising edge will be an ?odd? second. the CMX910 will calculate the error in the sample counter latched in from the ?even? utc second and will apply the required correction to the sample counter at the nex t nudge_trigger point. a nudge_done interrupt is then generated, indicating that sample c ounter alignment has been achieved. auto nudge track (slot_sample_control b1-0 = 10). in th is mode, the CMX910 calculates the correction needed for the sample counter once per second (on the rising edge of utc1pps). ?odd? and ?even? utc seconds are treated differently: if 320 sample_count < 960 when the rising edge of utc1pps occurs, the CMX910 assumes it to be an ?odd? utc second and calculates a sample nudge value of (640 - samp le_count). otherwise, the sample nudge value is calculated as (-1 sample_count). this calculated value (or max_auto_nudge, whichever is smaller in magnitude) is then added to the sample counter at the next nudge_trigger point. note: if the c writes a non-zero value to the slot _nudge register when in auto nudge track mode, this will be added to the slot counter at the same time that the sample counter value is updated. the slot_nudge register gets auto-cleared after bei ng used which causes a nudge_done interrupt, otherwise nudge done interrupts are not generated in auto nudge track mode. the max_auto_nudge register is used to limit the magnitude of the allowed nudge in order to avoid potential timing problems. the max_auto_nudge register is ignored in manual nudge and auto nudge acquire mode. the typical sequence of events that the c must perform to achieve and retain slot and sample counter synchronisation (using auto nudge) is shown below: a) if the device has just come out of reset, initialise nudge_trigger (see section 5.4.4) and max_auto_nudge registers. b) wait for an even utc second to occur, t hen put the CMX910 into auto nudge acquire mode. c) wait for a nudge done interrupt, then put the CMX910 into auto nudge track mode. d) wait for the next utc1pps rising edge, then read the slot_sample_utc1pps register, and use this to determine the error in the slot counter (the sample counter should be correctly aligned at this point). write the necessary co rrection to the slot_nudge register. e) wait for a nudge done interrupt. both slot and sample counters will now be correctly aligned, and the c can proceed with ais rx and tx operat ions, as required. no further nudge done interrupts will be generated while in auto nudge tra ck mode unless slot_nudge is written to again. f) continue monitoring the utc time signal. if the CMX910 slot and sample counters become misaligned for any reason (for instance, when a ut c leap second occurs), the c must perform another synchronisation sequence. if a direct utc ti me signal becomes lost for any reason, then the c must switch the CMX910 to manual nudge mode and maintain synchronisation to a utc indirect source or an appropriate base station. 5.4.3 sleep mode the rx1 and rx2 channels are individua lly configurable using bits in the receiver control registers rx1_control and rx2_control. when enabled for ais re ception, it is possible to reduce power consumption significantly by configur ing the CMX910 to automatically turn off its internal receiver circuits
ais baseband processor CMX910 ? 2009 cml microsystems plc 18 d/910/6 and negate the enab1 or enab2 pins during inacti ve slots. this will happen when sleep mode is enabled and a valid training sequence and start flag has not been det ected at the beginning of a slot, i.e. there is no data to demodulate. the rx1 and rx2 circuits w ill automatically power up again at the end of an inactive slot, ready to search for another training sequence in the next slot. note that when sleep mode is enabled, the rx1 and rx2 channels power down independently; it is possible for either, or both, channels to be powered down in any particular slot, depending on the activity in the channels. the sleep mode feature is enabled by setting bit 2 of t he slot_sample_control register. the period within an inactive slot that the rx circuits are to be disabled must be programmed by the c into the sleep_sample and wakeup_sample register s: sleep mode starts within an inactive slot when the sample counter equals the value in the sleep_sample regi ster and finishes when the sample counter subsequently reaches the value in the wakeup_sample register. the value in the sleep_sample register should be loaded with a sample number just beyond the latest point in a slot that the training sequence and start flag could occur. account must be taken of the maximum remote transmitter timing error and distance del ay, as well as the local receiver timing error and filter delays. the value in the wakeup_sample register can be chos en to be towards the end of the inactive slot, or shortly after the beginning of the next slot. when det ermining the value to write to wakeup_sample, account must be taken of the maximum remote transmitte r timing error, as well as the local receiver timing error and receive circuit start-up time. 5.4.4 selecting the nudge_trigger value whether the sample counter tracking is perfo rmed using manual nudge mode or auto nudge mode, the value written to the nudge_trigger register needs to be chosen carefully to avoid confusing the transmit or receive event timing. all transmission events are timed relative to a point befor e the start of the slot in which a message is to be transmitted. this point is defined by the sample value loaded into the tx_start par ameter in the tx event sequence table (described in section 5.5.5). at this point the transmission is deem ed to have started. all subsequent transmit events within the slot are timed rela tive to this tx_start point. this means that once transmission starts, all subsequent events (e.g. pa rampi ng, start of modulation) occur with the correct relative timing until the whole slot has been transmi tted, irrespective of any change to sample_count. therefore the only transmit problem that may occur is if a sample counter nudge causes the value in sample_count to skip past the point defined by tx_start, which would c ause the event to be missed. this can be prevented by limiting the maximum allow ed nudge value and ensuring that the nudge_trigger is far enough away from tx_start that sample_c ount can never skip past the tx_start event. similarly, all receive events are timed relative to the point that a start flag is detected after a valid training sequence, so once reception of a data packet begins , changes to sample_count will not affect the received data. the c should be aware, however, that any values reported in the rx1_sample, rx1_slot, rx2_sample and rx2_slot registers are t he values that were in the slot and sample counters at the time that the rx1 and rx2 start flags were detected. to avoid confusion it is therefore advisable to ensure that nudge_trigger is sufficiently far away from the likely position of a start flag. also, if the receive channels are configured to sleep during inactive slots (i.e. slot_sample_control b2 = 1), the nudge_trigger value must be far enough away from sleep_sample and wakeup_sample values that the sample_count can never ski p past these events (this would c ause intermittent receive channel malfunction). a further restriction is that the value added to the sample counter must not cause an overflow. this means that in manual nudge mode the c should ensure that 0 (nudge_trigger + sample_nudge) 1279. in auto nudge track mode, ensure that 0 (nudge_trigger max_auto_nudge) 1279.
ais baseband processor CMX910 ? 2009 cml microsystems plc 19 d/910/6 5.5 transmit operation the CMX910 is capable of transmitting ais data in either raw mode or burst mode, and can also be configured for dsc transmission (fsk 1200 baud). ais ca rrier sensing (cstdma) for class b systems is supported, as is a mechanism to allow two or mo re messages to be chained into consecutive slots. a block diagram of the transmit data path is shown in figure 6. in ais raw mode and dsc mode, data is passed dire ctly from the tx fifo to the g(m)fsk/fsk modulator, so the c will be responsible for s ending any necessary training sequence and performing hdlc processing and nrzi coding for ais, or other dat a coding for dsc. when configured in ais burst mode, the CMX910 uses a secondary internal mess age buffer to assemble an entire message (up to 5 slot) to which it automatically adds the traini ng sequence, start/stop flags, crc, bit stuffing and nrzi coding prior to transmission. in either case, the c must indicate how many data bits the message contains in the tx_bits register, and in which slot to power up the exte rnal tx circuits in the tx_slot register. after setting up the appropriate registers, tr ansmission is initiated by writing to a bit in the tx_control register. tx_fifo_threshold tx_status tx_slot tx_control cstdma_threshold tx_bits tx_fifo hdlc/ nrzi encoder 172 byte message buffer g(m)fsk/ fsk modulator and filters ? dac ? dac itxp itxn qtxn qtxp i q (32 bytes) ais burst ais raw, dsc reconstruction filters c-bus enab0 dac ramp slot count sample count tx timing control enab4 enab5 special command interface tx event sequence table figure 6 transmit channel 5.5.1 transmitter registers tx_fifo register: 8-bit write only (data-streaming). c-bus address $20 32 byte tx channel fifo, emptied on re set. supports c-bus data streaming. bit: 7 6 5 4 3 2 1 0 tx channel data byte tx_fifo_threshold register: 8-bit write only. c-bus address $21 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 000 tx fifo threshold level the transmit fifo threshold register is used to set the level at which a ?fifo nearly empty? warning is triggered. if the number of bytes in tx_f ifo is less than or equal to the value in bits 4- 0 of threshold register then the fifo trigger flag (bit 7 of tx_status) will be set to 1. this can also be used to generate an interrupt. bits 7-5 of tx_fifo_threshold should be set to 0.
ais baseband processor CMX910 ? 2009 cml microsystems plc 20 d/910/6 tx_status register: 16-bit read only. c-bus address $22 register gets set to $0080 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx over- flow tx under- flow tx fifo fill level tx fifo trigger 0 0 0 tx state tx_status register b15: tx overflow this bit gets set high if the c attempts to write to the tx fifo when it is already full, indicating that data has been lost. a tx overflow does not automatically cause the transmission to be aborted, this must be done separately by the the c if necessary. the tx overflow bit gets cleared as soon as the tx_status register has been read. tx_status register b14: tx underflow this bit gets set high if the c does not send data to the CMX910 quickly enough during transmission, causing a data famine in the tx channel (this does not happen in ais burst mode since an entire message must be conveyed to the CMX910 before transmission starts). a tx underflow does not automatically cause the transmission to be aborted, this must be done by the the c. failure to do this will result in erroneous data being transmitted. the tx underflow bit gets cleared as soon as it has been read. note: tx_status b15 and b14 are ored together for the purpose of generating an interrupt. tx_status register b13-8: tx fifo fill level this shows how many bytes are in the tx fifo. the number will be in the range 0 to 32. tx_status register b7: tx fifo trigger this bit will be high if the tx fifo fill level is less than or equal to the tx threshold level, i.e. tx_status[13-8] tx_fifo_threshold[4-0]. this bit can generate an interrupt. tx_status register b3-0: tx state indicates the current transmitter state. if a tr ansmission has not been reques ted the tx state will be idle , otherwise the tx state bits change to refl ect the progress of the transmission. after a transmission has completed the tx state bits w ill either indicate that the transmission was successful, or will indicate the nature of any problem encountered. b3 b2 b1 b0 0 0 0 0 idle 0 0 0 1 building message buffer (burst mode) 0 0 1 0 message buffer ready (burst mode) 0 0 1 1 tx pending 0 1 0 0 tx in progress 0 1 0 1 tx aborted ? carrier sensed (cstdma) 0 1 1 0 tx aborted ? buffer not ready (burst mode) 0 1 1 1 tx aborted ? message too long (burst mode) 1 0 0 0 chained message in progress
ais baseband processor CMX910 ? 2009 cml microsystems plc 21 d/910/6 tx_slot register: 16-bit write only. c-bus address $23 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 0000 slot number in which to begin a transmission sequence the tx_slot register must be loaded with the slot number in which a transmit sequence begins. typically this will be one or two slots before the slot in which data is to be transmitted, allowing time for the external rf circuits to power up and stabilise. further details about transmit timings are provided in section 5.5.5. tx_bits register: 16-bit write only. c-bus address $24 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 number of bits to transmit in ais burst mode, the tx_bits r egister must be programmed with the total number of data bits in the message excluding all of the training sequence, star t/end flags, crc and bit stuffing bits added by the CMX910. in ais burst mode the num ber loaded into tx_bits should always be a multiple of 8 since the ais specification require s that the data payload (prior to hdlc coding) be a whole number of bytes. in ais raw mode or dsc mode, t he tx_bits register must be pr ogrammed with the total number of data bits in the message including all of the training sequence, start/end flags, crc and bit stuffing bits (ais mode) or other data coding bi ts (dsc mode). this number will generally not be a multiple of 8, in which case the last byte sent by the c through the tx fifo must be padded with trailing zeroes. tx_control register: 16-bit write only. c-bus address $25 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 0000000 tx start cs- tdma enable cs- tdma chan tx mode tx fifo clear tx state reset tx_control register b8: tx start setting b8 = 1 causes a transmission to be triggered in the slot specified in the tx_slot register. this bit will be automatically cleared as soon as the transmission is complete. tx_control register b7: cstdma enable set b7 = 1 for carrier sensing tdma operation, b7 = 0 for normal operation. tx_control register b6: cstdma channel select determines which receive channel is examined for presence of a carrier before the transmit operation starts. set b6 = 1 to select cstdma operation on ?channel 2?, or b6 = 0 for operation on ?channel 1?.
ais baseband processor CMX910 ? 2009 cml microsystems plc 22 d/910/6 tx_control register b5-2: tx mode b5 b4 b3 b2 0 0 0 0 ais raw mode, 25khz channel 0 0 0 1 ais raw mode, 12.5khz channel 0 0 1 0 dsc mode 0 0 1 1 reserved, do not use 0 1 0 0 ais burst mode, 25khz channel 0 1 0 1 ais burst mode, 12.5khz channel 0 1 1 0 reserved, do not use 0 1 1 1 reserved, do not use 1 0 0 0 ais test mode, 25khz c hannel (transmit data supplied by c) 1 0 0 1 ais test mode, 12.5khz c hannel (transmit data supplied by c) 1 0 1 0 dsc test mode (transmit data supplied by c) 1 0 1 1 reserved, do not use 1 1 0 0 ais test mode, 25khz channel (internal prbs transmitted) 1 1 0 1 ais test mode, 12.5khz channel (internal prbs transmitted) 1 1 1 0 dsc test mode (internal prbs transmitted) 1 1 1 1 reserved, do not use the tx mode bits select the modulation schem e and (ais) channel spacing to use. the CMX910 automatically configures its in ternal modulators and channel filters for whichever transmit mode is selected: ? ais (25khz channel) = gmsk with a bt-produc t of 0.4 and a modulation index of 0.5. ? ais (12.5khz channel) = gfsk with a bt-produc t of 0.3 and a modulation index of 0.25. ? dsc = 1200 baud fsk, with frequency modulation of a 1700hz sub-carrier and a pre- emphasis of 6db/octave. the frequency sh ift is between 1300hz (logic 1) and 2100 hz (logic 0). for both ais and fsk operation, setting b5=1 puts the CMX910 into transmit test mode: this causes data to be transmitted immediately, without waiting for the next transmit trigger point as in normal transmit modes. transmitted test data can be configured to come from the c through the tx fifo, or from an internally generated pseudo-random bit sequence. no data coding or insertion of training sequences will be carried out, and the CMX910 will not attempt to perform rf control using the enab pins and dac0 ramping; transmission will continue until transmit test mode is cleared by the c. note that when any test mode is enabled, it is essential that tx_control b8 = 0. tx_control register b1: tx fifo clear data written to this bit does not get stored; inst ead, writing a 1 to this bit generates a reset pulse which empties the tx fifo and resets the tx fifo fill level (tx_status b13-8) to zero. tx_control register b0: tx state reset immediately after power up, the tx channel must be initialised by writ ing a 1 to the tx state reset bit of tx_control. writing a 1 to the tx state reset bit can also be done at any other time in order to cause any pending or active transmission to be terminated ? this causes the pa and transmit hardware to be switched off, any internal states related to tx to be cleared and the internal message buffers (ais burst mode) to be wiped. the tx fifo will not be cleared by writing a 1 to this bit, that can be done if necessary by writing a 1 to tx_control bit 1. note: when a 1 is written to this bit, a delay of at least 250 s is r equired for the CMX910 to reset the transmit channel before the tx_control regist er is written to again.
ais baseband processor CMX910 ? 2009 cml microsystems plc 23 d/910/6 cstdma_threshold register: 16-bit write only. c-bus address $26 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cstdma signal strength threshold the value in the cstdma_threshold register is used when attempting a transmission with cstdma enabled. at the beginning of the slot in which data is to be transmitted, typically just before the pa is ramped up, the received signal strength in the selected cstdma channel (rx1 or rx2) is measured. if this exceeds the value in the cstdma_threshold register, the transmission is aborted and a txdone interrupt is generated. otherwise, transmission proceeds normally. note: the value written to the cs tdma_threshold register must be between 0 and 32767 ($7fff). the received signal strength is calculated by a ccumulating the i/q vector magnitudes at each sample point (i.e. every 20.833s) between t he cstdma_start and cs tdma_end points, as defined in the tx event sequenc e table (see section 5.5.5). before being added to the running total, each vector magnitude is multiplied by a fixed gain of 0.4117 and a user-programmable gain ?cstdma_gain? of between 0 and 1 (this is set up using a special command function, see section 5.12). in the case of overflow, the accumulat ed signal strength value saturates at 32767 ($7fff). the total accumulated signal strength value is given by: + = ? ? ? ? ? ? + = end cstdma start cstdma n nn gain cstdma qi strength signal cstdma _ 1_ 22 _ 4117.0 __ for the purpose of calculating the cstdma signal strength, the signed 16-bit i and q vector values are taken directly from the output of the selected channel?s - adcs, prior to passing through the channel filters. with a dc voltage of 1.7v (differential) applied to the input of the i or q adc, the corresponding i or q adc output will be approximately 15000.
ais baseband processor CMX910 ? 2009 cml microsystems plc 24 d/910/6 5.5.2 ais raw mode transmit in ais raw mode, transmit data is passed directly from the tx fifo to the g(m)fsk modulator. apart from the tx fifo, no buffering is performed inside the cmx 910. the c must calculate the entire transmitted message including the training sequence, hdlc proc essing (start/stop flags, bit stuffing, and crc insertion) and nrzi coding. note: in ais raw mode, data written to tx_fifo is transmitted most significant bit first. the ais message structure, however, requires each message byte to be output least significant bit first. the c must therefore ensure that dur ing the process of hdlc processing and nrzi coding that the resulting data bytes are correctly reversed. the c is expected to perform the following sequence of operations in order to transmit a data packet in raw mode: ? initialise the transmitter timing registers as descr ibed in section 5.5.5. (this only needs to be done once after the device has come out of reset). ? check that the tx state flags in the tx_status register indicate that the transmitter is in the idle state and that the tx fifo does not contain data from an earlier aborted transmission. if necessary, the transmitter state machine can be re set and tx_fifo can be cleared by writing 1 to tx_control register b1-0. ? write the total number of bits to be transmitted into the tx_bits register (not necessarily a multiple of 8, because of bit stuffing). ? write the timing reference slot number to tx_slot (this will most likely be a one or two slots before the slot in which to transmit data, to allow ti me for the external tx circuits to power up). ? prime the tx fifo with at least one byte of tr ansmit data, up to the entire message if it fits. unused bits in the last byte should be padded with zeroes ? note that data written to the tx_fifo in ais raw mode is transmitted most significant bit first. ? request a transmission by writing to the tx start bit in the tx_control register. ? feed any remaining data bytes to the tx fifo as they are required, then wait for a tx done interrupt and check the transmitter state in the tx_status register to determine if the transmission was successful. the actions of the CMX910 are: ? if the tx state is cleared by the c, the external rf circuits are turned off if necessary (dac0 ramped down and then enab0, 4 and 5 negated, assuming the CMX910 has control of these functions). the tx state then becomes idle . ? upon receiving a tx start request, the CMX910 not es the tx_slot and tx_bits values and sets the tx state to tx pending . ? when the requested transmit point a rrives, the tx state changes to tx in progress and the external transmit circuits are enabled accordi ng to how the transmit timing is configured. ? at the end of a transmitted message the pa ramps down. if the tx_fifo is empty at this point the tx state changes to idle , a tx done interrupt is generated, and the external rf circuits get disabled. if the tx_fifo is not empty, the cm x910 assumes a chained message is being sent; it notes the length of this new me ssage (in tx_bits), and leaves the external rf circuits enabled. the tx state then changes to chained message , then to tx in progress when transmission of the new message begins in the following slot. note that if cstdma mode is active and a carrier is sensed in the selected channel at the beginning of the requested transmit slot, the transmi ssion is aborted (tx state changes to tx aborted, carrier sensed ) ? this causes a tx done interrupt to be generated. data in tx_fifo is retained, so the c can choose to issue a tx state reset and clear tx_fifo, or reschedule the transmission in another slot. in ais raw mode, if data is fed to tx_fifo too slowly then the tx underflow bit in the tx_status register gets set high, or if more data is written than tx_fifo can accommodate then the tx overflow bit gets set high. in either case, a tx fifo error interrupt gets generated, but transmission continues. the response of the c should be to reset the tx state and clear tx_fifo by setting tx_control b0 and b1 high. this prevents erroneous data from being transmitted.
ais baseband processor CMX910 ? 2009 cml microsystems plc 25 d/910/6 idle tx pending tx in progress tx abort, carrier sensed chained message tx s tate reset tx start reissued cstdma active, carrier sensed tx done interrupt tx complete, tx fifo not empty tx complete, tx fifo empty tx done interrupt tx start issued start point reached figure 7 tx (ais raw mode) state transitions 5.5.3 ais burst mode transmit in ais burst mode, an entire message is transferred to the CMX910 prior to transmission. the CMX910 then processes the data by performing bit stu ffing, nrzi encoding and addition of training sequence, start/stop flags and crc checksum as required by ais. the resulting bit stream is held in a secondary message buffer within the CMX910. this message pr ocessing must be complete before transmission is allowed to begin, so it is not possible to get a tx underflow error in ais burst mode. note: in ais burst mode, the data bytes are automatically transmitted least significant bit first as required by the ais specification. the c is expected to perform the following sequenc e of operations in order to transmit an ais data packet in burst mode: ? initialise the transmitter timing registers as descr ibed in section 5.5.5. (this only needs to be done once after the device has come out of reset). ? check that the tx state flags in the tx_status register indicate that the transmitter is in the idle state and that tx_fifo does not contain data from an earlier aborted transmission. if necessary, the transmitter state machine can be reset and tx_f ifo can be cleared by writing 1 to tx_control register b1-0. ? write the total number of data bits to be transmitt ed into the tx_bits register. this should be the number of data bits in the packet excluding any bit stuffing bits, flags, crc checksum or training sequence. the ais specification requires th is number to be a multiple of eight. ? load the whole (up to 5 slot) message into the CMX910 through tx_fifo. ? write the timing reference slot number to tx_slot (this will most likely be a one or two slots before the slot in which to transmit data, to allow ti me for the external tx circuits to power up). ? request a transmission by writing to the tx start bit in the tx_control register. ? wait for a tx done interrupt, then check the tr ansmitter state in the tx_status register to determine if the transmission was successful.
ais baseband processor CMX910 ? 2009 cml microsystems plc 26 d/910/6 the actions of the CMX910 during a successful transmission will be: ? if a tx state reset is performed by the c, the ex ternal rf circuits are turned off if necessary (dac0 ramped down and enab0, 4, 5 negated, a ssuming the CMX910 has control of these functions). the tx state bits in t he tx_status register then indicate idle . ? as soon as data is written to the tx_fifo, the CMX910 will begin assembling a packet for transmission in its internal message buffer. du ring this operation, the tx state indicates building message buffer . ? when the CMX910 has assembled a complete transmit packet (including training sequence and hdlc coding), if a tx start has already been issued the tx state changes to tx pending , otherwise the tx state changes to message buffer ready and waits for tx start to be issued before going to tx pending . ? when the requested transmit point a rrives, the tx state changes to tx in progress and the external transmit circuits are enabled accordi ng to how the transmit timing is configured. ? at the end of a transmitted message the pa ramps down. if the tx_fifo is empty at this point the tx state changes to idle , a tx done interrupt is generated, and the external rf circuits get disabled. otherwise the CMX910 assumes a chained message is being sent; it notes the length of this new message (in tx_bits), leaves the ex ternal rf circuits enabled, and builds a new message (during which time tx state first changes to chained message for approximately 20s then to building message buffer , then to tx pending ). this message is transmitted in the following slot, during which time tx state indicates tx in progress . a number of error conditions are checked for duri ng ais burst mode transmit, each of which causes transmission to be aborted and a tx done interrupt to be generated. the associated tx states are: 1. tx aborted, message too long : this happens if the internal message buffer is not big enough for the hdlc coded data (should not happen in normal operation, as the message buffer is big enough for a 5-slot message). this condition requi res the c to issue a tx state reset. 2. tx aborted, buffer not ready : this happens if the requested tx start point arrives before the message buffer is ready. the c can then choose to issue a tx state reset or to carry on building the message and reschedule the transmission in another slot. 3. tx aborted, carrier sensed : this happens if cstdma mode is ac tive and a carrier is sensed in the selected channel at the beginning of the request ed transmit slot. data in the message buffer is retained, so that the c can choose to issue a tx state reset or to reschedule the transmission in another slot. it is not possible to get a tx_fifo underflow in ai s burst mode, but writing too quickly could cause an overflow (this sets the tx overflow bit in the tx_status register), caus ing a tx fifo error interrupt to be generated. the contents of the message buffer will bec ome corrupted by the overflow but the transmit operation will continue, so the c should abort the tr ansmission (i.e. reset the tx state and clear tx_fifo by setting tx_control b0 and b1 high). there is a possibility that the CMX910 will add enough st uffing bits to a message in ais burst mode to cause the message to overrun into the next sl ot, although there is enough padding in the ais slot structure to ensure that this occurrence is extremely rare. a minor slot overrun is not normally considered to be a problem in the ais system, but if this happens when the CMX910 is attempting to chain a message in the next slot, it is possible that the CMX910 will miss the chained message start event. this will cause the chained message to be transmitted one slot too late. to enable the c to recognise if this error condition is about to happen, the special command ?read_message_length? (section 5.12) is provided that allows the c to determine the tota l number of message bits that have been created in the CMX910?s internal message buffer. when this spec ial command is issued, the CMX910 waits until the message buffer is complete then generates a ?specia l command done? interrupt. the c can then read the total number of message bits from the spc_out 0 register; which includes the training sequence, start/stop flags, crc checksum and stuffing bits, as well as the actual message bits. the c should also take into account the magnitude of any nudge t hat may be performed during the transmission to determine whether the message is too long to allow chaining to be attempted.
ais baseband processor CMX910 ? 2009 cml microsystems plc 27 d/910/6 idle building message buffer tx abort, message too long buffer overflow tx done interrupt tx abort, buffer not ready message buffer ready tx pending tx in progress tx abort, carrier sensed chained message tx start has been issued, start point reached tx done interrupt message complete, tx start has been reissued message complete, tx start not yet reissued message complete, tx start has been issued write to tx fifo tx s tate reset tx start reissued cstdma active, carrier sensed tx done interrupt tx complete, tx fifo not empty tx complete, tx fifo empty tx done interrupt tx start issued start point reached message complete, tx start not yet issued buffer overflow tx done interrup t figure 8 tx (ais burst mode) state transitions 5.5.4 dsc transmit dsc transmission operates in a similar way to ais raw mode: transmit data is passed directly from the tx fifo to the fsk modulator and filters. apart from the tx fifo, no buffering is performed inside the CMX910. the c must calculate the entire dsc transmit message including the dot pattern and phasing sequence, and all subsequent message and checksum words (both dx and rx characters). note: in dsc mode, data written to tx_fifo is transmitted least significant bit first . the c is expected to perform the following sequence of operations in order to transmit a dsc message: ? initialise the transmitter timing registers as descr ibed in section 5.5.5. (this only needs to be done once after the device has come out of reset). ? check that the tx state flags in the tx_status register indicate that the transmitter is in the idle state and that the tx fifo does not contain data from an earlier aborted transmission. if necessary, the transmitter state machine can be re set and tx_fifo can be cleared by writing 1 to tx_control register b1-0. ? write the total number of bits to be transmitted into the tx_bits register. ? write the timing reference slot number to tx_slo t (this will most likely be one or two slots before the slot in which to transmit data, to allow ti me for the external tx circuits to power up).
ais baseband processor CMX910 ? 2009 cml microsystems plc 28 d/910/6 ? prime the tx fifo with at least one byte of tr ansmit data, up to the entire message if it fits. unused bits in the last byte should be padded with zeroes ? note that data written to the tx_fifo in dsc mode is transmitted least significant bit first. ? request a transmission by writing to the tx start bit in the tx_control register. ? feed any remaining data bytes to the tx fifo as they are required, then wait for a tx done interrupt and check the transmitter state in the tx_status register to determine if the transmission was successful. the actions of the CMX910 are: ? if the tx state is cleared by the c, the external rf circuits are turned off if necessary (dac0 ramped down and then enab0, 4 and 5 negated, assuming the CMX910 has control of these functions). the tx state then becomes idle . ? upon receiving a tx start request, the CMX910 not es the tx_slot and tx_bits values and sets the tx state to tx pending . ? when the requested transmit point a rrives, the tx state changes to tx in progress and the external transmit circuits are enabled accordi ng to how the transmit timing is configured. ? at the end of a transmitted message the pa ramps down, the tx state changes to idle , a tx done interrupt is generated, and the exter nal rf circuits get disabled. in dsc mode, if data is fed to tx_f ifo too slowly then the tx underflow bit in the tx_status register gets set high, or if more data is written than tx_fifo c an accommodate then the tx ov erflow bit gets set high. in either case, a tx fifo error interrupt gets generated, but transmission conti nues. the response of the c should be to reset the tx state and clear tx _fifo by setting tx_control b0 and b1 high. this prevents erroneous data from being transmitted. idle tx pending tx in progress tx s tate reset tx complete tx done interrupt tx start issued start point reached figure 9 tx (dsc mode) state transitions
ais baseband processor CMX910 ? 2009 cml microsystems plc 29 d/910/6 5.5.5 transmitter timing control the CMX910 can be easily configured to control the timing of transmission events. this includes the enabling of external rf circuits (e.g. synthesisers and power amplifier), as well as the time at which internal data modulation begins. the flexibility of this timing control allows the CMX910 to be straightforwardly adapted to the charac teristics of the rf transmit circuits, such as the power up time or synthesiser lock time. the control of the external rf transmit circuits is effected through three of the device enable port digital output pins (enab0, 4, 5) along with the dac0 ramping function. a b rf power s lot start s lot start time 100% figure 10 typical ais transmission a typical ais transmission is shown in figure 10. the CMX910 starts timi ng transmit ?power-up? actions relative to point a, which will typically be in a slot prior to the one in which transmission is to occur ? this allows external rf transmit circuits time to power up and stabilise. at the end of a transmission, a sequence of ?power-down? actions is performed. the CMX910 times these ?power-down? actions relative to the last message bit having been modulated, shown as point b in figure 10. in that way differences in message length due to bit stuffing, and multiple-s lot messages, are automatically accommodated. point a in figure 10 occurs in the slot defined in the c-bus tx_slot register. the absolute sample number at which point a occurs within the slot, along with the relative timings of all of the subsequent transmit events, are configured as a table of val ues that are communicated to the CMX910 using a special command interface operation (section 5.12) ? this operation must be performed before any transmissions are attempted. typically, this will only need to be done once as part of an initialisation routine. all timings are measured in units of ?sample times?, each of which lasts for one fifth of an ais bit period (1/5 1/9600 ? 20.833s). the transmit sequence consists of several different types of event. these are: ? changes to the external hardware, done through the tx device enable pins enab0, 4, 5 (typically used to turn the rf on/off, tx on/off, and pa on/off) and the triggering of the dac0 ramp up/down. ? trigger for the start/end of the cstdma peri od (only has an effect if cstdma is enabled). ? timing trigger for the start and end of the data modulation. ? a chained message start and end event to allow for ais transmission in consecutive slots without a full switch off in-between. ? a dummy event in case any of the abov e are not required in the application. the transmit event sequence is programmed as follows: 1. apply special command ?load_tx_sequence? ( $10). this readies the CMX910?s tx event sequence table to accept data. 2. write the tx_start sample value into the spc_i n0 register and the enab0-5 pin reset state into spc_in1, then apply special command ?poke2_inc? ($08) . this copies the data into the internal tx event sequence table. 3. for the remaining fourteen transmit events, load the event number into spc_in0 and the delay (relative to the previous event) into spc_i n1, and apply special command ?poke2_inc? ($08). the
ais baseband processor CMX910 ? 2009 cml microsystems plc 30 d/910/6 events must be loaded in chronological order, with a minimum delay of 1 sample period between consecutive events (maximum delay = 32767). all fourteen of these ev ent slots must be filled; if certain transmit events are not required, t hey should be replaced with the dummy event. 4. apply special command ?setup_tx_sequence? ($0f ). this causes the CMX910 to process the table of tx events and conf igure its internal transmit logic accordingly. note that when the start sample (tx_ start) is reached within tx_slot, the CMX910 inserts a fixed delay of four samples ? this is in addition to the delay specified for the first event in the sequence table. also note that the last six events specifi ed in the sequence table are timed fr om the end of the last message bit being fed to the internal modulator. the transmit events and their code numbers are as follows: rf_on 1 pin enab0 is asserted. tx_on 2 pin enab4 is asserted. pa_on 3 pin enab5 is asserted. dac0_rampup 4 dac0 begins ramping up (used for pa ramp up control). cstdma_start 5 defines the star t of the cstdma sensing window. cstdma_end 6 defines the end of the cstdma sensing window. modulate_start 7 data modulation begins. (tx data fed to internal filters). modulate_end 8 data modulation ends; reference for power down events. dac0_rampdown 9 dac0 begins ramping down. pa_off 10 pin enab5 is negated. tx_off 11 pin enab4 is negated. rf_off 12 pin enab0 is negated. dummy 13 no action. chained_message_start 14 the start of t he sub-sequence repeated for chained messages. chained_message_end 15 the end of the s ub-sequence repeated for chained messages. for the duration that enab5 is asserted (i.e . between the pa_on and pa_off events) the CMX910 turns off the three rx control lines (enab1-3), and disables its internal rx1/rx2 circuits. it is intended that during this period the external tx/rx swit ch for the antenna switches to select tx. when calculating the modulate_start timing value, the delay through the CMX910?s internal transmit filters and any external components must be taken into account to ensure that data bits appear on-air at the correct time (the filter delays are specified in section 7). the modulate_end event has an in-built delay of 46 sample times to allow the last bit to make its way out of the transmit filter. allowance must be made for this built-in delay, as well as for the del ay through any external components, when calculating the timing of the transmit power down events. because all actions subsequent to tx_start effectively use relative timings, they will not be disturbed by any sample counter ?nudge? that may occur during tr ansmission. it is important, however, to ensure that any ?nudge? that occurs does not cause the sample c ounter to skip past the tx_start point, which would cause the transmission to be missed. a working example of how to set up a transmit event sequence is shown in table 2 (the order of events and delay timings shown are for illustrative purposes only):
ais baseband processor CMX910 ? 2009 cml microsystems plc 31 d/910/6 parameter spc _in0 spc _in1 explanation tx_start sample value and enab0-5 pin reset state 500 0 the transmit sequence starts at sample number 500 in a slot. the enab0-5 pins will be set to 0 on a reset or a command to start the tx sequence, i.e. they are all active high. tx_on 2 5 after the initial 4 sample delay, insert another 5 sample delay then assert the tx control line (enab4). rf_on 1 790 insert 790 sample delay then assert the rf control line (enab0). cstdma_start 1,3 5 20 insert 20 sample delay then st art monitoring the chosen rx input for a signal which will cause an abort (if cstdma enabled). cstdma_end 1,3 6 32 insert 32 sample delay then stop cstdma monitoring. pa_on 3 15 insert 15 sample delay then assert the pa control line (enab5). at this point, the th ree rx control lines (enab1-3) are negated. chained_message_start 1,2 14 1 insert 1 sample delay then plac e a marker for the point at which the sequence will restart if a consecutive tx message is needed. dac0_rampup 4 6 insert 6 sample delay then initia te the dac0 ramp-up (for ais, the transmitted signal will be carrier only at this point) modulate_start 1,2 7 8 insert 8 sample delay then st art feeding data to the transmit modulator and filters. at this point during a transmission the CMX910 feeds the entire message to the tr ansmit modulator bit-by-bit. all subsequent transmit events are timed relative to t he end of the last message bit, indicated by the modulate_end event. dac0_rampdown 4 9 1 insert 1 sample delay then initiate the dac0 ramp-down. modulate_end 1,2 8 10 insert 10 sample delay then define the ?end- of-modulation? point (?b? in figure 10 ). between modulate_start and modulate_end there are (message bits 5) +46 samples for ais, or (message bits 40) + 46 samples for fsk. chained_message_end 1,2 15 30 insert 30 sample delay. if more data is present in tx_fifo, chain a second (or third?) message on. pa_off 10 6 insert 6 sample delay then negat e the pa control line. at the same time, the three rx c ontrol lines (enab1-3) are reasserted. tx_off 11 7 insert 7 sample delay then negate the tx control line. rf_off 12 8 insert 8 sample delay then negate the rf control line. notes: 1. it is essential that the cstdma, chained_message and modulate start events precede their associated end events, otherwise undesirabl e results will be obtained. 2. modulate_start must come after chain ed_message_start and modulate_end must come before chained_message_end for consecutiv e messages to work. modulate_start and chained_message_start must appear in the first group of eight timed ev ents, modulate_end and chained_message_end must appear in the final group of six. 3. it is intended that cstdma only operat es in the period prior to the actual on-air transmission of the first in a sequence of chained messages. both cstdma_start and cstdma_end should come before pa_on and dac0_rampup, otherwise cstdma will not operate correctly. also, the delay between cstdma_start and cstdma_end must be 7. 4. in this example dac0_rampdown is specified before modulate_end in the last group of six events, so the dac0 ramp-down begins prior to the modulate_end point ? with the values shown, the dac0 ramp- down starts 10 samples before modulate_end. table 2 example tx event sequence setup
ais baseband processor CMX910 ? 2009 cml microsystems plc 32 d/910/6 5.6 receive operation the CMX910 has two main receive channels (rx1 and rx 2) which are capable of receiving ais data in either raw mode or burst mode, and either of which may be configured for dsc reception (fsk 1200 baud). alternatively, an external fsk demodulator may be interfaced to the CMX910, allowing simultaneous reception of two ais channels and one dsc channel. the rx1 and rx2 channels can be configured and operated independently. g(m)fsk/ fsk filters and demodulator ? adc ? adc i q channel filters anti-alias filters rx1_fifo_threshold rx1_status rx1_slot rx1_bytes rx1_sample rx1_fifo (32 bytes) irx1p irx1n qrx1n qrx1p rx1_control rx1_freqerr rx1_rssi c-bu s hdlc/ nrzi decoder raw burst ais dsc 172 byte message buffer #2 172 byte message buffer #1 rx1 control slot count sample count sleep control enab1 g(m)fsk/ fsk filters and demodulator ? adc ? adc i q channel filters anti-alias filters rx2_fifo_threshold rx2_status rx2_slot rx2_bytes rx2_sample rx2_fifo (32 bytes) irx2p irx2n qrx2n qrx2p rx2_control rx2_freqerr rx2_rssi hdlc/ nrzi decoder raw burst ais dsc 172 byte message buffer #2 172 byte message buffer #1 rx2 control enab2 fsk_fifo_threshold fsk_status fsk_control fsk_fifo (32 bytes) int. ext. external fsk interface enab3 fsk_rxd fsk_mute fsk_det slot count sample count sleep control figure 11 receive channel
ais baseband processor CMX910 ? 2009 cml microsystems plc 33 d/910/6 5.6.1 receiver registers rx1_fifo register: 8-bit read only (data-streaming). c-bus address $30 rx2_fifo register: 8-bit read only (data-streaming). c-bus address $40 fsk_fifo register: 8-bit read onl y (data-streaming). c-bus address $50 independent 32 byte receive channel fifos, empt ied on reset. support c-bus data streaming. bit: 7 6 5 4 3 2 1 0 $30: rx1 channel data byte $40: rx2 channel data byte $50: fsk channel data byte rx1_fifo and rx2_fifo are used to transfer ais data to the c from the rx1 and rx2 channels respectively. fsk_fifo is used to transfer fsk data to the c from whichever channel is enabled for dsc reception (either the rx1 channel, rx 2 channel or the external fsk interface). rx1_fifo_threshold register: 8-bit write only. c-bus address $31 rx2_fifo_threshold register: 8-bit write only. c-bus address $41 fsk_fifo_threshold register: 8- bit write only. c-bus address $51 all registers set to $1f on reset. bit: 7 6 5 4 3 2 1 0 $31: reserved, set to 000 rx1 fifo threshold level $41: reserved, set to 000 rx2 fifo threshold level $51: reserved, set to 000 fsk fifo threshold level the receive fifo threshold registers are used to set the level at which a ?fifo nearly full? warning is triggered for each of the three receive channel fifos. if the number of bytes in a fifo is greater than the value in bits 4-0 of the asso ciated threshold register then the fifo trigger flag (bit 7 of the associated status register) will be set high. these flags can also be used to generate interrupts. bits 7-5 of the threshold registers should be set to 0. rx1_status register: 16-bit read only. c-bus address $32 rx2_status register: 16-bit read only. c-bus address $42 fsk_status register: 16-bit read only. c-bus address $52 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $32: rx1 over- flow rx1 under- flow rx1 fifo fill level rx1 fifo trigger 0 0 0 0 rx1 state $42: rx2 over- flow rx2 under- flow rx2 fifo fill level rx2 fifo trigger 0 0 0 0 rx2 state $52: fsk over- flow fsk under- flow fsk fifo fill level fsk fifo trigger 0 0 0 0 0 0 0 rx1/rx2/fsk_status register b15: overflow these bits get set high if the c does not r ead the associated fifo quickly enough and allows it to overflow, causing received data to be lost. each overflow bit gets cleared as soon as the associated status register is read.
ais baseband processor CMX910 ? 2009 cml microsystems plc 34 d/910/6 rx1/rx2/fsk_status register b14: underflow these bits get set high if the c attempts to read from the associated fifo when it is already empty. the rx1/rx2/fsk underflow bits get cleared as soon as the associated status register is read. note: each receive channel status register has b15 and b14 ored together for the purpose of generating an interrupt. rx1/rx2/fsk_status register b13-8: fifo fill level this shows how many bytes are in the associat ed fifo. the number will be in the range 0 to 32. rx1/rx2/fsk_status register b7: fifo trigger these bits will be high if the associated fifo fill level is greater than the threshold level, i.e. these bits can generate an interrupt. ? rx1 fifo trigger is set high if (rx1_s tatus[13-8] > rx1_fifo_threshold[4-0]) ? rx2 fifo trigger is set high if (rx2_s tatus[13-8] > rx2_fifo_threshold[4-0]) ? fsk fifo trigger is set high if (fsk_st atus[13-8] > fsk_fifo_threshold[4-0]) rx1/rx2_status register b2-0: ais state indicates the current state of the rx1 and rx2 channel (ais only). b2 b1 b0 0 0 0 idle 0 0 1 receiving 0 1 0 error: message too long or missing end flag (burst mode) 0 1 1 error: crc mismatch (burst mode) 1 0 0 error: new frame header found but both message buffers full (burst mode) 1 0 1 error: end flag not on byte boundary (burst mode) rx1_slot register: 16-bit read only. c-bus address $33 rx2_slot register: 16-bit read only. c-bus address $43 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $33: slot number in which a valid training s equence + start flag was detected in channel rx1 $43: slot number in which a valid training s equence + start flag was detected in channel rx2 rx1_sample register: 16-bit read only. c-bus address $34 rx2_sample register: 16-bit read only. c-bus address $44 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $34: sample number in which a valid training sequence + start flag was detected in channel rx1 $44: sample number in which a valid training sequence + start flag was detected in channel rx2 when receiving an ais message on the rx1 channel, the CMX910 writes the time at which the last bit of the start flag is detected into t he rx1_slot and rx1_sample r egisters (this is only done if a the start flag is preceded by a valid training sequence). the rx2_slot and rx2_sample registers perform the same function for the rx2 channel. note: the delay through the CMX910?s internal filters mean that the reported slo t/sample number will be approximately 52 sample periods (10.4 bit periods) later than the arrival time of the last bit of the start flag at the device pins.
ais baseband processor CMX910 ? 2009 cml microsystems plc 35 d/910/6 rx1_bytes register: 16-bit read only. c-bus address $35 rx2_bytes register: 16-bit read only. c-bus address $45 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $35: number of message bytes received in channel rx1 (ais burst mode only) $45: number of message bytes received in channel rx2 (ais burst mode only) registers rx1_bytes and rx2_bytes are only used in ais burst mode and indicate the number of message bytes that are available for the c to read out. rx1_control register: 8-bit write only. c-bus address $36 rx2_control register: 8-bit write only. c-bus address $46 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 $36: rsvd, set to 0 rx1 dc offset correction rx1/2 burst enab rx1 mode rx1 fifo clear rx1 state reset $46: rsvd, set to 0 rx2 dc offset correction rsvd, set to 0 rx2 mode rx2 fifo clear rx2 state reset rx1/rx2_control register b6-5: dc offset correction these bits are used to independently configure t he i/q dc offset correction mode for the rx1 and rx2 channels. b6 b5 0 0 i/q dc offset correction: reset and hold 0 1 i/q dc offset correction: hold 1 0 i/q dc offset correction: run slowly 1 1 i/q dc offset correction: run quickly rx1_control register b4: rx1 and rx2 burst mode enable bit 4 of the rx1_control register is used to select between burst and raw mode operation for both the rx1 and rx2 channel (ais only): b4 = 1 for burst mode, b4 = 0 for raw mode. rx1/rx2_control register b3-2: rx1 and rx2 mode these bits are used to independently configur e the modulation type for the rx1 and rx2 channels. b3 b2 0 0 ais, 25khz channel 0 1 ais, 12.5khz channel 1 0 dsc 1 1 reserved, do not use rx1/rx2_control register b1: fifo clear data written to these bits do not get stored; instead, writing a 1 to either of these bits generates a reset pulse which clears the rx1 or rx2 fifo and resets the fifo fill level (rx1_status or rx2_status b13-8) to zero.
ais baseband processor CMX910 ? 2009 cml microsystems plc 36 d/910/6 rx1/rx2_control register b0: rx state reset immediately after power up, the rx1 and rx2 channel s must be initialised by writing a 1 to bit 0 (rx state reset) of the rx1_cont rol or rx2_control registers. wri ting a 1 to the rx state reset bits can also be done at any other time in order to immediately terminate an active reception in that channel and to cause the rx st ate (ais raw or burst mode) to revert to ?idle?. any internal states related to receive will be cleared and the in ternal message buffers (ais burst mode) will be wiped. the receive fifos are not cleared by writing a 1 to the rx state reset bits, that can be done if necessary by writing a 1 to rx1_control bit 1 or rx2_control bit 1 (a is raw/burst mode) or fsk_control bit 1 (dsc mode). note: after a 1 is written to bit 0 of the rx1_control (or rx2_control), it will take up to 250s before t hat channel is reset properly and data stops being written to the associated fifo (r x1_fifo, rx2_fifo, or fsk_fifo). only after that time should the fifo be cleared or the rx1_control (or rx2_control) register be written to again. rx1_freqerr register: 16-bit read only. c-bus address $37 rx2_freqerr register: 16-bit read only. c-bus address $47 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $37: rx1 channel frequency error (hz) $47: rx2 channel frequency error (hz) registers rx1_freqerr and rx2_freqerr are only valid for ais burst mode reception, and indicate the frequency error of the received carrier (relative to the local oscillator) in units of hertz. the values are calculated from the received trai ning sequence and start flag and are reported in 2?s complement format. rx1_rssi register: 16-bit read only. c-bus address $38 rx2_rssi register: 16-bit read only. c-bus address $48 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $38: rx1 channel rssi $48: rx2 channel rssi registers rx1_rssi and rx2_rssi are valid for ai s burst and raw mode reception, and indicate the signal strength of the receiv ed carrier. the rssi values are calculated over a specified window within each slot, as set up by the ?r ssi_window? special command function (see section 5.12). the rssi values are calculated by accumulating the i/q vector magnitudes from the associated channel filter outputs at each sample point (i .e. every 20.833s) over the specified window. before being added to the running total, each vector magnitude is multiplied by a fixed gain of 0.4117 and a user-programmable gain ?rssi_gain? of between 0 and 1 (this is also set up using a special command function). in the case of over flow, the accumulated rssi value saturates at 32767 ($7fff). the total accumulated signal strength value is given by: ?+ = ? ? ? ? ? ? + = 2 _ _ 22 _ 4117.0 length startrssi startrssin nn gainrssi qi rssi with a dc voltage of 1.7v (differential) applied to the input of the i or q adc, the corresponding i or q channel filter output will be approximately 30000.
ais baseband processor CMX910 ? 2009 cml microsystems plc 37 d/910/6 rx1_rssi register: 8-bit read only. c-bus address $38 rx2_rssi register: 8-bit read only. c-bus address $48 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 $38: rx1 channel rssi $48: rx2 channel rssi registers rx1_rssi and rx2_rssi are only valid fo r ais burst mode reception, and indicate the signal strength of the received carrier in units of db (an i/q vector magnitude of 0.5v at the device pins will give an rssi value of approximately 112) . the values are calculated from the received training sequence and start flag. fsk_control register: 8-bit write only. c-bus address $53 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 000000 fsk fifo clear en fsk i/f fsk_control register b1: fsk fifo clear data written to this bit does not get stored; inst ead, writing a 1 to this bit generates a reset pulse which clears the fsk fifo and resets the fsk fifo fill level (fsk_status b13-8) to zero. fsk_control register b0: enable fsk interface setting b0 = 1 enables the external fsk interface circuit, allowing serial data from the fsk_rxd pin to be packed into bytes and transferred to the c via the fsk_fifo (subject to the fsk_det and fsk_mute pins being in the correct state) . if b0 = 0, data will instead be loaded into the fsk_fifo from whichever, if either, of the ma in rx1 or rx2 receive channels is configured for dsc reception. 5.6.2 ais raw mode receive the operation of receive channel rx1 in ais raw mode is described below (the operation of receive channel rx2 in ais raw mode is essentially identical to that of rx1, but is controlled through its own individual c-bus registers). in ais raw mode the CMX910 searches the rx1 channel for a header (training + start flag sequence) to detect the start of a message, then transfers the rece ived data (starting with the three training bytes and the start flag, then all subsequent dem odulated bytes) directly to rx1_fif o as soon as available. this byte stream continues even after the end of a me ssage and in the absence of a received signal (the data will then be indeterminate), but will cease while the rx1 channel is sleeping (section 5.4.3). resynchronisation of the rx1 data stream occurs each time the CMX910 detects a valid training sequence and start flag on the channel (at which poi nt the rx1_slot and rx1_sample registers are updated) but no other indication is given that valid me ssages are being received; it is the responsibility of the c to detect the training and start flag bytes in the received data stream, and to perform all hdlc/nrzi decoding, crc checking and end flag detection. bit ordering of the received bytes in ais raw mode is the same as in tx ais ra w mode, i.e. the received bits are packed into bytes most significant bit first . as the ais message structure requires message bytes to be transmitted least significant bit first, the c must ensure that during the process of hdlc/nrzi decoding that the resulting data by tes are correctly reversed. dependi ng on the configuration of the remote transmitter, one of four different types of nrzi encoded training bytes may be received ? this
ais baseband processor CMX910 ? 2009 cml microsystems plc 38 d/910/6 situation arises because the ais spec ification allows a transmitter?s nrzi encoder to start in either of its two quiescent states, and the pre-nrzi encoded training bytes can also be one of two different types ($55 or $aa). therefore, for any particular message, the three received training bytes in ais raw mode will all be either $33, $66, $99 or $cc, although the firs t few bits may be corrupted depending on the power-up characteristics of the remote trans mitter and local receiver circuits. in ais raw mode, whenever an rx1 state reset is performed (by setting rx1_control b0 = 1) the channel state (rx1_status b2-0) becomes idle. this changes to receiving when the first valid training sequence and start flag have been detected, where it re mains until another rx1 state reset occurs. 5.6.3 ais burst mode receive the operation of receive channel rx1 in ais burst mode is described below (the operation of receive channel rx2 in ais burst mode is essent ially identical to that of rx1). in ais burst mode the rx1 channel st ate (rx1_status b2-0) changes to receiving when a valid training sequence and start flag are detected. the CMX910 then performs nrzi decoding and bit destuffing on the received data stream, and calc ulates the crc checksum. at t he end of the message the receive channel state changes from receiving to either idle or one of four error states (below). at the same time, an ?rx1 state alert? interrupt is flagged. the four error conditions that the CMX910 can detect in a received message (in burst mode) are: 1. message too long or missing end flag . this indicates that the received message, after bit destuffing, is too long to fit into an internal 172 byte message buffer. this condition could be caused by a missing or corrupted end flag. 2. crc mismatch . this indicates that the received frame checksum does not match that calculated by the CMX910, most probably as t he result of one or more message bits being corrupted. 3. new frame header found but both message buffers full . this happens if both internal message buffers are in use when another message arri ves. this is caused by a failure of the c to read the received messages out quickly enough. 4. end flag not on byte boundary . this indicates that the received message, after bit destuffing, is not a multiple of 8 bits. assuming that the message was transmitted correctly, the most probable cause of this error is an end flag being missed due to noise, and a subsequent message?s start flag being misidentif ied as the expected end flag. if one of these four error conditions is detected in a received message the CMX910 discards the message data and, after flagging the ?rx1 state alert? interr upt, continues searching for the next training sequence and start flag. if a message with no error is found the rx1 channel state changes from receiving to idle (causing an ?rx1 state alert? interrupt); the decoded message, comprising the three training sequence bytes, start flag, message payload, end flag and crc bytes, is then copied to one of the CMX910?s internal message buffers. when its turn comes around to be read out, an ?r x1 burst available? interrupt is generated. at this point the CMX910 updates the registers rx1_slot, rx1_sample, rx 1_bytes, rx1_freqerr and rx1_rssi with the values calculated for that message, then begins transferring the data from the internal message buffer to rx1_fifo. note: a new message will only generate an ?rx1 burst available? interrupt when any previous message has been read out from rx1_fifo in its entirety. for any particular message, the three received (nrz i-decoded) training bytes in ais burst mode will all be either $55 or $aa depending on the configuration of t he remote transmitter, although the first few bits may be corrupted depending on the power-up characteristi cs of the remote transmitter and local receiver circuit s.
ais baseband processor CMX910 ? 2009 cml microsystems plc 39 d/910/6 5.6.4 dsc receive (main channel) either the rx1 or rx2 channel can be configured for dsc reception. the CMX910 first applies 6db/octave de-emphasis to the received signal, then demodulates the resulting 1200 baud nrz fsk data. only one of the channels at a time must be configured for dsc reception. the received data is packed into 8-bit bytes for forward transmission to the c. the CMX910 makes no attempt to align data bits within the bytes or perform dot pattern or data phasing detection, those functions must be performed by the host c. no attempt is made to correctly align data, it is simply packed into bytes (least significant bit first) as it arrives. note: when the rx1 or rx2 channel is configured for dsc operation, the received data is forwarded to the c through fsk_fifo, not rx1_fifo or rx2_fifo. this prevents the dsc reception from corrupting any ais data that may still be present in rx1_fifo or rx2_fifo. 5.6.5 dsc receive (external fsk interface) the CMX910?s external fsk interface retimes as ynchronous nrz fsk data from an external 1200 baud demodulator such as the fx604, and is intended for use as a third parallel receive channel for dsc reception in the case that both of the main receive channels are assi gned to ais operation. the data from the external fsk demodulator is applied to the f sk_rxd pin and gets packed into 8-bit bytes (least significant bit first) before being loaded into fsk_fi fo for forward transmission to the c. the CMX910?s fsk interface circuit does not align data bits within the bytes or perform dot pattern or data phasing detection, those functions must be performed by the host c. two further input pins are provided to prevent data from being decoded in the absence of a valid fsk signal: the fsk_mute input is intended for connecti on to the dsc radio sub-system, and should go high to indicate no received signal; the fsk_det input is intended for connection to the fsk demodulator and indicates that valid fsk data is being received. data will only be written to the fsk fifo if fsk_mute = 0 and fsk_det = 1. the CMX910 samples data on the fsk_rxd pin half a bit period after each transition (i.e. in the middle of a received bit), and every bit period thereafter unt il another transition occurs. a transition on the fsk_rxd pin should occur at least once in every ten bit periods in order to maintain reliable synchronisation with the incoming bit stream. the cmx 910?s data retiming circuit can tolerate an error of 1.5% in the input data baud rate.
ais baseband processor CMX910 ? 2009 cml microsystems plc 40 d/910/6 5.7 auxiliary a-to-d converter a 10-bit adc is provided to assist in a variety of measurement and control functions. the adc includes an internal sample-and-hold circuit and is designed to produce a digital output proportional to the analogue supply (av dd ), full scale being the positive supply. an input multiplexer allows the input to be selected from one of five sources. three of t hese inputs (adcs 2, 1 and 0) are provided with an uncommitted op-amp, each of which can be disabled if required. there are five adc data output registers (adc4-0), one for each adc channel. control and digital data output is via the c-bus. the auxiliary adc can be operated in either single-s hot mode, where the c can initiate a single conversion of each enabled adc channel, or in auto convert mode, where the enabled adc channels are converted in a continuous loop. by default, the time taken to convert each adc channel is (529 48)s 11.021s. in addition to this, at the beginning of a si ngle-shot conversion or when auto convert mode is first enabled, two dummy conversion cycles ( 22.042s) are performed befor e any actual conversion begins, allowing time for the adc?s internal bias circuits to power up and settle. the conversion rate can be altered using one of the CMX910?s special commands (section 5.12). the adc and its sample-and-hold automatically power down when not in use. the three uncommitted op- amps are only powered down when they are disabl ed, using bits in register adc_control2. auxadc2fb auxadc2n auxadc2p en op amp 2 auxadc1fb auxadc1n auxadc1p en op amp 1 auxadc0fb auxadc0n auxadc0p en op amp 0 auxadc3 au xad c 4 adc1 adc2 adc3 adc4 c -bu s adc_control2 adc_status adc0 adc_control1 op amp enable signals (adc_convert) figure 12 auxiliary adc adc0 data register: 16-bit read only. c-bus address $60 adc1 data register: 16-bit read only. c-bus address $61 adc2 data register: 16-bit read only. c-bus address $62 adc3 data register: 16-bit read only. c-bus address $63 adc4 data register: 16-bit read only. c-bus address $64 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $60: 0 0 0 0 0 0 adc0 data $61: 0 0 0 0 0 0 adc1 data $62: 0 0 0 0 0 0 adc2 data $63: 0 0 0 0 0 0 adc3 data $64: 0 0 0 0 0 0 adc4 data
ais baseband processor CMX910 ? 2009 cml microsystems plc 41 d/910/6 adc_control1 register: 8-bit write only. c-bus address $65 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 00 auto conv. en adc4 en adc3 en adc2 en adc1 en adc0 adc_control1 register b5: adc auto convert setting b5 = 1 causes the adc to continuously convert the enabled channels in ascending order. while in auto convert mode, the channel enable bi ts (adc_control1 b4-0) can be changed at any time, and will update the adc conversion scheduler i mmediately. auto convert is terminated by setting b5 = 0. adc_control1 register b4-0: enable adc4-0 writing a 1 to these bits selects the corresponding adc channels for conversion. adc_control2 register: 8-bit write only. c-bus address $66 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 00000 en op amp2 en op amp1 en op amp0 adc_control2 register b2-0: enable op amp 2-0 the three uncommitted op-amps are independently cont rollable using these bits: setting a bit to 1 enables the uncommitted op-amp in the corres ponding adc channel; setting the bit to 0 powers down the corresponding op-amp and puts its output into a high impedance state. when an op- amp is powered down, its ?output? pin (a uxadc2fb, auxadc1fb, and auxadc0fb) may be used as an input to the adc. adc_status register: 8-bit read only. c-bus address $67 reset state is $01. bit: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 adc ready adc_status register b0: adc ready this bit goes low when a single-shot conversion is started using the adc_convert command, and remains low until conversions on all enabled adc channels have completed. this bit can be polled by the c to find out when the conversion sequence has completed; it is also connected to the interrupt generator block. this bit does not go low when auto convert mode is enabled, or if an adc_convert command is issued while auto convert mode is enabled. adc_convert command (no data) c-bus address $68 issuing this c-bus command causes a single-shot conv ersion to be initiated in which a single conversion is done on each of the enabled adc channels in ascending order. this command is ignored if it is issued while the adc is in auto convert mode.
ais baseband processor CMX910 ? 2009 cml microsystems plc 42 d/910/6 5.8 auxiliary d-to-a converters the CMX910 is provided with five general purpose 10-bit digital-to-analogue converters (dac0?4) to assist in a variety of control functions. these dacs are independent of each other, and can be individually enabled or powered down. the dacs are designed to provide an output as a proportion of the analogue supply voltage, depending on the dac?s data register setti ng: a value of 0 drives that dac?s output to av ss ; a value of 1023 (3ff 16 ) drives the output to av dd . dac0 has an additional ramp mode feature. with this mode enabled, t he contents of an internal 64 word 10 bit dac ram can be transferred in ascendi ng order to the dac0 data register (a ramp-up sequence), or in descending order (a ramp-down sequence). the rate at which the dac ram contents are copied to dac0 can be programmed through the c-bus register dac0_timestep . the dac0 ramp-up and ramp-down facility is particularly useful for cont rolling the profile of the transmitter power at the beginning and end of a transmit slot, in order to mini mise adjacent-channel splatter. the dac0 ramp-up and ramp-down can be initiated automat ically by the CMX910 as part of its transmit event sequencer, or can be configured through the dac_control register to operate via the cbus commands dac0_rampup and dac0_rampdown. the default contents of the dac ram c an be changed by first putting dac0 into dac ram load mode . this resets the internal dac ram address pointer to 0. the ram contents can then be modified by repeatedly writing to c-bus location dac_ram_load ? the address pointer is aut omatically incremented after each word that is written. dac0 dac1 dac2 dac4 dac3 c-bus dac_control (dac0_rampdown) (dac0_rampup) dac0_timestep dac0_ram_load a uxdac0 a uxdac1 a uxdac2 a uxdac 3 a uxdac4 aux dac control logic 64 x 10 ram dac enable signals dac0 ramp mode figure 13 auxiliary dacs
ais baseband processor CMX910 ? 2009 cml microsystems plc 43 d/910/6 dac0 data register: 16-bit write only. c-bus address $70 dac1 data register: 16-bit write only. c-bus address $71 dac2 data register: 16-bit write only. c-bus address $72 dac3 data register: 16-bit write only. c-bus address $73 dac4 data register: 16-bit write only. c-bus address $74 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $70: reserved, set to 000000 dac0 data (written by c-bus, or from dac ram in ramp mode) $71: reserved, set to 000000 dac1 data $72: reserved, set to 000000 dac2 data $73: reserved, set to 000000 dac3 data $74: reserved, set to 000000 dac4 data dac_control register: 8-bit write only. c-bus address $75 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 dac ram load c-bus ramp control dac0 ramp mode en dac4 en dac3 en dac2 en dac1 en dac0 dac_control register b7: dac ram load setting b7 = 1 to this bit causes dac0 to i mmediately enter dac ram load mode, causing the internal dac ram address pointer to be rese t to 0. the dac ram can then be loaded by repeatedly writing data to the c-bus dac_ram _load register. while in dac ram load mode, any attempt to write directly to the dac0 data register will be ignored, as will any attempt to initiate a ramp-up or ramp-down sequence (whether issued automatically by the CMX910 or from the c-bus). as soon as the c has finished loading the dac ram, dac_control register b7 can be taken low again. dac_control register b6: c-bus ramp control if dac0 is in ramp mode, the state of this register bit determines how the ramp-up and ramp- down functions are controlled: b6 = 0 for automatic control by the CMX910, b6 = 1 for control via the c-bus commands dac0_rampup and dac0_rampdown. dac_control register b5: dac0 ramp mode setting dac_control b5 = 1 at the same time as dac_control b7 = 0 puts dac0 into ramp mode. the internal dac ram address pointer immediatel y gets reset to 0, an initial read of the dac ram is performed and the resulting data is transferr ed to the dac0 data register. the circuit then responds to any subsequent ramp-up and ramp-down commands. while in ramp mode, any attempt to write directly to the dac0 data regist er will be ignored, as will any attempt to write to the dac ram using the dac_ram_load register. note: if both dac_control b7 = 0 and b5 = 0, the c is able to write directly to the dac0 data register, and any ramp-up or ramp-down commands or attempts to write to the dac ram will be ignored: b7 b6 b5 0 x 0 dac0 data register c an be written directly by c 0 0 1 dac0 in ramp mode, autom atically controlled by the CMX910 0 1 1 dac0 in ramp mode, controlled by the c 1 x x dac0 in dac ram load mode
ais baseband processor CMX910 ? 2009 cml microsystems plc 44 d/910/6 dac_control register b4-0: enable dac4-0 writing a 1 to these bits powers up the corre sponding dac analogue circuit, writing a 0 powers down the dac and puts the dac output pin into a high impedance state. dac0_rampup command (no data) c-bus address $76 dac0_rampdown command (no data) c-bus address $77 these two commands are enabled only if dac_control register b7-5 = 011. in that case, issuing a dac0_rampup command causes dac0 to begin ramping up (ram[0 63] copied to dac0 data register), and dac0_rampdown causes dac0 to begin ramping down (ram [63 0] copied to dac0 data register). if a dac0_rampup command is issued while dac0 is in the process of ramping down, or vice-versa, the ramp process i mmediately reverses direction. the CMX910 ignores any dac0_rampup commands iss ued when dac0 is already ramped up, or any dac0_rampdown commands issued when dac0 is already ramped down. dac0_timestep register: 8-bit write only. c-bus address $78 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 dac0 ramp timestep the contents of the dac0_timestep register determine the rate at which the dac ram data is transferred to the dac0 data register during a ramp-up or ramp-down sequence: time between each data transfer = (dac0_timestep + 1) 0.25s the time taken for the entire ramp-up or ramp -down process to complete is therefore: t ramp = 63 ( dac0_timestep + 1) 0.25s
ais baseband processor CMX910 ? 2009 cml microsystems plc 45 d/910/6 dac_ram_load register: 16-bit write onl y (data-streaming). c-bus address $79 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved, set to 000000 dac ram data the contents of the dac ram c an be modified by writing to t he dac_ram_load c-bus register (only the least significant 10 bits are used). to do this, the device must first be put into dac ram load mode by setting dac_control b7 = 1 (this rese ts the internal ram address pointer to 0). after each 10-bit word is written to the da c ram the internal ram address pointer is automatically incremented, ready for the next word to be entered. a total of 64 data writes to dac_ram_load are necessary to modify the ent ire ram contents, beginning at ram address 0 and finishing at address 63. afterwards, the c must set dac_control b7 = 0 to exit dac ram load mode. the dac_ram_load register supports c-bus data-streaming. the dac ram contents default to a raised cosine profile: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?= 63 cos1 2 1023 n y n default dac ram contents after reset (hexadecimal) 0 000 1 001 2 003 3 006 4 00a 5 010 6 017 7 01f 8 028 9 033 10 03e 11 04b 12 059 13 068 14 078 15 089 16 09a 17 0ad 18 0c1 19 0d5 20 0ea 21 100 22 116 23 12d 24 145 25 15d 26 175 27 18e 28 1a7 29 1c0 30 1d9 31 1f3 32 20c 33 226 34 23f 35 258 36 271 37 28a 38 2a2 39 2ba 40 2d2 41 2e9 42 2ff 43 315 44 32a 45 33e 46 352 47 365 48 376 49 387 50 397 51 3a6 52 3b4 53 3c1 54 3cc 55 3d7 56 3e0 57 3e8 58 3ef 59 3f5 60 3f9 61 3fc 62 3fe 63 3ff figure 14 ramdac values
ais baseband processor CMX910 ? 2009 cml microsystems plc 46 d/910/6 5.9 interrupt generator the CMX910 has sixteen internal interrupt sources which provide status information to the c ? these are accessible through a c-bus read register. the interr upt flags may also be enabled to drive the open-drain irqn output pin. interrupt register: 16-bit read only. c-bus address $80 register gets set to $0080 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spcl cmnd done aux adc done rx2 state alert rx1 state alert tx fifo error fsk fifo error rx2 fifo error rx1 fifo error tx fifo trigger fsk fifo trigger rx2 fifo trigger rx1 fifo trigger tx done rx2 burst avail. rx1 burst avail. nudge done interrupt register b15: special command done this bit goes high to indicate that a comm and issued to the special command interface has completed. this bit gets cleared automatically after being read. interrupt register b14: aux adc done this bit goes high to indicate that the auxilia ry adc has finished doing a sequence of conversions after an adc_convert command was issued. this bit gets cleared automatically after being read. interrupt register b13: rx2 state alert this bit goes high in ais burst mode only, and indicates that the rx2 channel has finished receiving a message ? the rx2_status register can be read to determine whether a valid message was received or an error occurred. this bit gets cleared automatically after being read. interrupt register b12: rx1 state alert this bit goes high in ais burst mode only, and indicates that the rx1 channel has finished receiving a message ? the rx1_status register can be read to determine whether a valid message was received or an error occurred. this bit gets cleared automatically after being read. interrupt register b11: tx fifo error this bit goes high to indicate that an overflow or an underflow error has occurred in the tx channel fifo. this can be determined by reading the tx_status register (bits 15 and 14). this bit gets cleared automatically after being read. interrupt register b10: fsk fifo error this bit goes high to indicate that an overflow or an underflow error has occurred in the fsk channel fifo. this can be determined by reading the fsk_status register (bits 15 and 14). this bit gets cleared automatically after being read. interrupt register b9: rx2 fifo error this bit goes high to indicate that an overflow or an underflow error has occurred in the rx2 channel fifo. this can be determined by reading t he rx2_status register (bits 15 and 14). this bit gets cleared automatically after being read. interrupt register b8: rx1 fifo error this bit goes high to indicate that an overflow or an underflow error has occurred in the rx1 channel fifo. this can be determined by reading t he rx1_status register (bits 15 and 14). this bit gets cleared automatically after being read.
ais baseband processor CMX910 ? 2009 cml microsystems plc 47 d/910/6 interrupt register b7: tx fifo trigger this bit is connected directly to tx_status b7, and goes high to indicate that the tx fifo fill level has dropped below a user-defined threshold (tx_status[13-8] tx_fifo_threshold[4-0]). note that this bit is level triggered, it does not get cleared by being read. interrupt register b6: fsk fifo trigger this bit is connected directly to fsk_status b7, and goes high to indicate that the fsk fifo fill level has exceeded a user-defined threshold (fsk_ status[13-8] > fsk_fi fo_threshold[4-0]). note that this bit is level triggered, it does not get cleared by being read. interrupt register b5: rx2 fifo trigger this bit is connected directly to rx2_status b7, and goes high to indicate that the rx2 fifo fill level has exceeded a user-defined threshold (rx 2_status[13-8] > rx2_fifo_threshold[4-0]). note that this bit is level triggered, it does not get cleared by being read. interrupt register b4: rx1 fifo trigger this bit is connected directly to rx1_status b7, and goes high to indicate that the rx1 fifo fill level has exceeded a user-defined threshold (rx 1_status[13-8] > rx1_fifo_threshold[4-0]). note that this bit is level triggered, it does not get cleared by being read. interrupt register b3: tx done this bit goes high to indicate that a transmit operation has completed or that an error condition has occurred. this bit gets clear ed automatically after being read. interrupt register b2: rx2 burst available this bit goes high to indicate that an ais packe t is available in channel rx2 (ais burst mode only). this bit gets cleared automatically after being read. interrupt register b1: rx1 burst available this bit goes high to indicate that an ais packe t is available in channel rx1 (ais burst mode only). this bit gets cleared automatically after being read. interrupt register b0: nudge done this bit goes high to indicate that a reques ted slot/sample nudge operation has been completed. this bit gets cleared automatically after being read. interrupt_enable register: 16-bit write only. c-bus address $81 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irqn en 15 irqn en 14 irqn en 13 irqn en 12 irqn en 11 irqn en 10 irqn en 9 irqn en 8 irqn en 7 irqn en 6 irqn en 5 irqn en 4 irqn en 3 irqn en 2 irqn en 1 irqn en 0 interrupt_enable register b15-0: interrupt enable bits the setting in this register determines which of t he bits in the interrupt register can cause a host c interrupt ? setting a bit high in the interrupt_e nable register allows the associated bit in the interrupt register to drive the irqn pin low. the interrupt_enable register can be written at any time, and can be used to enable or disable any combi nation of the sixteen interrupt sources. note: the value written to the interrupt_enable register does not affect the c ontents of the interrupt register. important notice: if an interrupt occurs whilst t he interrupt register is being read by the host controller, there is a possibility that the new interr upt may be lost. to minimi se the chances of this happening, it is recommended that the interrupt r egister should only be read when the irqn pin goes active (the interrupt register should not be polled). it is further recommended that when the host microcontroller is waiting for an in terrupt, a timeout routine is implemented.
ais baseband processor CMX910 ? 2009 cml microsystems plc 48 d/910/6 5.10 device enable port the device enable port (pins enab5 ? enab0) provides for the timed control of peripheral rf circuits that is required for tdma operation. the enab5 ? enab0 pins are digital outputs and will typically be used as enabling signals for the external receiver/transmitter ci rcuits and power amplifier. by default, the CMX910 will automatically control all six device enable pins. in conjunction with the automatic pa ramping feature of dac0, this greatly simplifies t he control of the rf circuits. if desired, individual pins of the device enable port may be configured to be under c control via the c-bus. enab register: 8-bit write only. c-bus address $90 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 00 enab 5 enab 4 enab 3 enab 2 enab 1 enab 0 enab register b5-0: enab5 ? enab0 data by writing to the bits in the enab register, the c can directly control the logic state of the corresponding enab5 ? enab0 pins. this only happens for those pins which have been configured to be under c-bus control, i.e. those whose corresponding bit in the enab_mask register is set high. note: if the corresponding bit in the enab_invert register is also set high, the logic level appearing at the device pin will be the inverse of the data in the enab register bit. enab_mask register: 8-bit write only. c-bus address $91 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 00 enab mask 5 enab mask 4 enab mask 3 enab mask 2 enab mask 1 enab mask 0 enab_mask register b5-0: enab5 ? enab0 mask each bit that is set high in the enab_mask r egister causes the corresponding device enable pin to be under direct control of the c. those bits in the enab_mask register that are low cause the corresponding pin to be under the autom atic control of the CMX910. enab_invert register: 8-bit write only. c-bus address $92 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 reserved, set to 00 enab invert 5 enab invert 4 enab invert 3 enab invert 2 enab invert 1 enab invert 0 enab_invert register b5-0: enab5 ? enab0 inversion control the polarity of the enab5 ? enab0 pins are i ndividually controlled through this register. by setting a bit high in the enab_invert register, the logic level appearing on the corresponding device enable pin will be inverted. this inversion is applied whether the pin is under c control or automatic CMX910 control.
ais baseband processor CMX910 ? 2009 cml microsystems plc 49 d/910/6 5.11 c-bus expansion port the c-bus expansion port facilitates the connection of the host c to as many as six additional c-bus compatible devices, while only requiring one additional c-bus chip select pin. to operate the expansion port, the c writes to the cb us_expand register through the cm x910?s normal c-bus port (sclk, cdata, csn) ? this can be done even when the cmx 910?s internal clocks are disabled. subsequently, for each bit set in bits 5-0 of the cbus_expand regi ster, taking the chip select expansion input (csxn) low will cause the associated exp5n ? exp0n output pi n to go low. each of the exp5n ? exp0n pins can be connected to the (active low) chip-select input of another c-bus compatible device. usually only one bit in the cbus_expand register would be set high at a time. setting more than one bit high may cause simultaneous selection of a number of c-bus devic es; in that case, care must be taken to avoid contention if a common rdata line is used. if expansion of the c-bus is not required, t he outputs exp5n ? exp0n can be used as general purpose digital outputs by holding csxn low and writing the required data pattern to the cbus_expand register. the data will then appear on the exp5n-exp0n pins in inverted form. cbus_expand register: 8-bit write only. c-bus address $a0 all bits cleared to 0 on reset. this register can be written while the CMX910?s internal clocks are disabled. bit: 7 6 5 4 3 2 1 0 reserved, set to 00 exp5n enab exp4n enab exp3n enab exp2n enab exp1n enab exp0n enab cbus_expand register b5-0: exp5n ? exp0n expansion bus enable each bit that is set to 1 causes the co rresponding exp5n ? exp0n output pin to be driven low when the csxn input pin is driven low. bits that are set to 0 cause the corresponding exp5n ? exp0n output pin to be held high.
ais baseband processor CMX910 ? 2009 cml microsystems plc 50 d/910/6 5.12 special command interface the special command interface allows the CMX910 to perform the special tasks defined below. the interface comprises two 16-bit write registers and a 16-bit read register for data transfers and an 8-bit write register which is used to instruct the CMX910 which special command to perform. when executing a special command that requires data to be transferred to the CMX910, the data must first be written to the spc_in0/1 registers, then the command code should be written to the special_command register. the act of writing to t he special_command register causes the CMX910 to begin processing the command, during which time the data in spc_in0, spc_in1 and special_command should not be changed. when the special command has completed, the ?special command done? bit in the interrupt register goes high and the special_command register gets cleared, and the returned data (if any) will be available in spc_out0. the CMX910 is then ready to accept another special command. spc_in0 register: 16-bit write only. c-bus address $b0 spc_in1 register: 16-bit write only. c-bus address $b1 spc_out0 register: 16-bit read only. c-bus address $b2 all bits cleared to 0 on reset. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $b0: special data in 0 (least signific ant data word used by special command) $b1: special data in 1 (most signific ant data word used by special command) $b2: special data out 0 (data word returned by special command) special_command register: 8-bit write only. c-bus address $b4 all bits cleared to 0 on reset. bit: 7 6 5 4 3 2 1 0 special command code the following special commands are available for use by the host c. unspecified commands are reserved for production test and should not be used. special command code spc_ in0 spc_ in1 spc_ out0 notes $04 (poke_inc) ? copies spc_in0 into an internal table then increments the internal address pointer. $08 (poke2_inc) ? ? copies spc_in0 and spc_in1 into two consecutive locations in an internal table then increments the internal address by 2. $0d (set_aux_adc_speed) ? sets aux adc convert time: t convert = ((22 spc_in0) + 1) 48 s (per channel). note: 24 spc_in0 256. $0f (setup_tx_sequence) causes the CMX910 to process the previously loaded table of tx events and configure its internal tx logic accordingly. $10 (load_tx_sequence) sets an internal address pointer to the base of the CMX910?s tx event sequence table, readying it to accept data. $12 (rssi_window) ? ? sets the window within a slot over which rx1 and rx2 rssi values are calculated. spc_in0 defines the rssi_start sample number, spc_in1 defines the rssi_length number, i.e. the number of samples to accumulate over.
ais baseband processor CMX910 ? 2009 cml microsystems plc 51 d/910/6 special command code spc_ in0 spc_ in1 spc_ out0 notes $14 (setup_gain) ? ? sets the gain factor to be applied to each sample when calculating rssi or cstdma signal strength: rssi_gain = spc_in0 32768 cstdma_gain = spc_in1 32768 note: the value written into spc_in0/1 must be between 0 and 32767 ($7fff). $17 (read_message_length) ? used in ais burst mode transmit only. waits until the message buffer is ready then reports back (in spc_out0) the total number of message bits created. $1f (eye_monitor) ? allows the rx1 and rx2 ?eye diagrams? to be monitored for diagnostic purposes. when enabled, this function drives the demodulated rx1 and rx2 channel signals onto the tx i and q output pins respectively. spc_in0 = $0000: disable eye_monitor spc_in0 = $0001: enable eye_monitor
ais baseband processor CMX910 ? 2009 cml microsystems plc 52 d/910/6 6. supplementary information 6.1 glossary of terms adc analogue-to-digital converter. ais automatic identification system, an ident ification, location and communication system using the maritime vhf radio band. baud the number of symbols transmitted per sec ond in a modulated signal. not necessarily the same as bits per second. bps bits per second, the speed at which bits are transmitted over a data channel. bt bandwidth-time product, equal to filter ?3db bandwidth (b) symbol time (t). c-bus cml's serial communication interface for peripheral devices. crc cyclic redundancy check, a type of error detecting code. cstdma carrier sense tdma, the channel access scheme used by ais class b. dac digital-to-analogue converter dc direct current, often used to refer to the static or unchanging part of a signal. dsc digital selective calling, an ear ly maritime communication system. fifo first in first out, a queue-based data buffer wher e data is output in the same order as it arrives. also known as an ?elastic buffer?. fsk frequency shift keying, a modulation scheme in which data symbols are represented by a shift in output signal frequency. galileo a satellite navigation system developed by the european union. gfsk gaussian frequency shift keying, an fsk modulation scheme with a gaussian filtered output signal. glonass global orbiting navigation satellite system , a satellite navigati on system developed by the commonwealth of independent stat es (former soviet republics). gmsk gaussian minimum shift keying, an fsk modulation scheme with a modulation index of 0.5 and a gaussian filtered output signal. gnss global navigation satellite system, a gener ic term for the gps, glonass and galileo satellite navigation systems. gps global positioning system, a satellite navigation system dev eloped by the u.s. department of defense. hdlc high-level data link control, a synchronous data link protocol adopted by the itu for use in ais. ic integrated circuit. imo international maritime organisation. itu international telecommunication union, an organisation established to standardise and regulate international radio and and telecommunications. c microcontroller nrz non return to zero, a binary data codi ng scheme where 1s and 0s are represented by distinct signal levels. nrzi non return to zero inverted, a binary data coding scheme where 1s cause no change in a transmitted signal level, and 0s cause a change (this is nrzi ?change on 0? as used in ais, as opposed to nrzi ?change on 1?). pa power amplifier. per packet error rate. prbs pseudo-random bit sequence, an apparently random stream of bits typically generated by a linear-feedback shift register.
ais baseband processor CMX910 ? 2009 cml microsystems plc 53 d/910/6 ram random access memory. rf radio frequency. rssi received signal strength indicator. rx receive or receiver spi serial peripheral interface, a common inter-chip serial communications interface. sotdma self organised tdma, the channel access scheme used by ais class a. tcxo temperature compensated crystal oscillator. tdma time division multiple access, a techni que for sharing access to a radio channel by dividing it into different time slots. tx transmit or transmitter utc universal time (coordinated), the official measure of time in the world. kept in synchronisation with the earth?s rotation by the introduction of occasional leap seconds. vhf very high frequency, itu band 8 (30 ? 300mhz) that includes the maritime mobile band. vqfn very thin profile quad flat no lead, an ic package type.
ais baseband processor CMX910 ? 2009 cml microsystems plc 54 d/910/6 7. performance specification 7.1 electrical performance 7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply (iov dd - av ss or dv ss ) -0.3 4.5 v voltage on any digital pin to dv ss -0.3 iov dd + 0.3 v voltage on any analogue pin to av ss -0.3 av dd + 0.3 current into or out of iov dd , av ss and dv ss pins -30 +30 ma current into or out of any other pin -20 +20 ma q1 package min. max. unit total allowable power dissipation at tamb = 25c 3500 mw ... derating 35.0 mw/c storage temperature -55 +125 c l9 package min. max. unit total allowable power dissipation at tamb = 25c 1690 mw ... derating 16.9 mw/c storage temperature -55 +125 c 7.1.2 operating limits correct operation of the device outsi de these limits is not implied. notes min. max. unit supply (iov dd ? av ss or dv ss ) 3.00 3.60 v operating temperature -40 +85 c
ais baseband processor CMX910 ? 2009 cml microsystems plc 55 d/910/6 7.1.3 operating characteristics for the following conditions unless otherwise specified: min./max. figures: iov dd = 3.0v to 3.6v, tamb = -40c to +85c. typ. figures: iov dd = 3.3v, tamb = 25c. load capacitance for digital outputs = 30pf. refclk = 19.2mhz. dc parameters notes min. typ. max. unit i iovdd (powersaved) 1 - 20 100 a i iovdd (fully operational) 1 - 35 60 ma av dd supply voltage 2.25 2.5 2.75 v dv dd supply voltage 2.25 2.5 2.75 v vbias reference voltage av dd /2 v current into vbias pin -0.1 - 0.1 a input logic ?1? level 70% - - iov dd input logic ?0? level - - 30% iov dd digital input leakage current (vin = 0 to iov dd ) -5.0 - 5.0 a input/output pin capacitance - - 15 pf output logic ?1? level @ i oh = -2ma 2 80% - - iov dd output logic ?0? level @ i ol = 3ma 2 - - 0.4 v 'off' state leakage current (vout = iov dd ) - - 10 a clock and timing parameters notes min. typ. max. unit refclk tolerance - - tbd ppm refclk mark:space ratio 35% - 65% utc1pps rising edge tolerance (wrt utc second) - - 5 s utc1pps ?high? pulse width 100 - - ns utc1pps ?low? pulse width 100 - - ns slotclkn pulse width - 20.833 - s csxn to exp[0-5]n propagation delay 0 - 25 ns c-bus timings ( figure 16 ) t cse csn-enable to clock-high time 100 - - ns t csh last clock-high to csn-high time 100 - - ns t loz clock-low to reply output enable time 0.0 - - ns t hiz csn-high to reply output 3-state time - - 1.0 s t csoff csn-high time between transactions 1.0 - - s t nxt inter-byte time 200 - - ns t ck clock-cycle time 200 - - ns t ch serial clock-high time 100 - - ns t cl serial clock-low time 100 - - ns t cds command data set-up time 75 - - ns t cdh command data hold time 25 - - ns t rds reply data set-up time 50 - - ns t rdh reply data hold time 0 - - ns
ais baseband processor CMX910 ? 2009 cml microsystems plc 56 d/910/6 transmit parameters notes min. typ. max. unit ais (gfsk 9600bps), 12.5khz channel bit rate accuracy - - 50 ppm bt - 0.3 - modulation index - 0.25 - storage time 3 - tbd - symbol ais (gmsk 9600bps), 25khz channel bit rate accuracy - - 50 ppm bt - 0.4 - modulation index - 0. 5 - storage time 3 - tbd - symbol dsc (fsk 1200bps, 6db/octave pre-emphasis) bit rate accuracy - - 50 ppm sub-carrier - 1700 - hz tx mark frequency - 1300 - hz tx space frequency - 2100 - hz modulation index - 2 - storage time 3 - tbd - symbol tx dac resolution - 14 - bits integral accuracy - - 2 lsb differential accuracy - - 2 lsb sinad 4 -65 -70 - db offset - - 20 mv gain matching, i to q - - 0.25 db phase matching, i to q - - 0.5 degree i, q output level 5 2.0 2.1 2.2 v
ais baseband processor CMX910 ? 2009 cml microsystems plc 57 d/910/6 receive parameters notes min. typ. max. unit ais (gfsk 9600bps), 12.5khz channel bit rate accuracy - - 50 ppm storage time 6 - tbd - symbol packet error rate (per) per with ?18db co-channel interference 12 - - 20% adjacent channel filtering 13 - -50 - db ais (gmsk 9600bps), 25khz channel bit rate accuracy - - 50 ppm storage time 6 - tbd - symbol packet error rate (per) per with ?10db co-channel interference 12 - - 20% adjacent channel filtering 13 - -70 - db dsc (fsk 1200bps, 6db/octave de-emphasis) bit rate accuracy - - tbd ppm sub-carrier - 1700 - hz tx mark frequency 1290 1300 1310 hz tx space frequency 2090 2100 2110 hz storage time 6 - tbd - symbol bit error rate (ber) at -10db co-channel interference 12 1% rx adc resolution - 16 - bits signal to noise 4 80 85 - db sinad 4 75 80 - db input impedance at 100hz 100 - - k differential input voltage 8 - 1.7 1.9 v pk-pk
ais baseband processor CMX910 ? 2009 cml microsystems plc 58 d/910/6 auxiliary adc notes min. typ. max. unit resolution - 10 - bits conversion time (per input) 9 11.021 - 117.35 s integral non-linearity 11 - - 4 bits differential non-linearity 11 - - 3 bits zero error (offset) - - 10 mv uncommitted op-amps: gain (no load) - 60 - db input offset - - 5 mv common mode input voltage 0 - av dd output current - - 125 a output voltage 0.5 - av dd -0.5 v capacitive load (including pin capacitance) - - 30 pf input noise voltage in 100hz ? 10khz bandwidth - 20 - v rms unity-gain bandwidth (no load) - 2.5 - mhz auxiliary dacs notes min. typ. max. unit resolution - 10 - bits settling time to 0.5 lsb 10 10 s output resistance - - 250 integral non-linearity - - 4 bits differential non-linearity - - 1 bits zero error (offset) - - 10 mv resistive load 5 - - k output noise voltage in 30khz bandwidth - 5 - v rms notes: 1. tamb = 25c, not including any current drawn from the device pins by external circuitry. 2. maximum total i ol for all outputs is 50ma, maximum total i oh for all outputs is 50ma. 3. through g(m)fsk/fsk transmit filter, dac, reconstruction filter and external rc filter. 4. measured with a 2.25khz te st signal in a 9khz bandwidth. 5. peak to peak differential, assuming av dd = 2.5v. level is proportional to av dd . 6. through external rc filter, anti-alias filter, a dc, channel filter, and g(m)fsk/fsk receive filters. 7. extrapolated from third harmonic distortion at maximum signal. 8. this means 0.425v (typ.) on eac h input of the differential pair. 9. programmable through the special command interface. 10. worst case large signal transition. 11. for signal levels between 0.5% and 99.5% of av dd . 12. tested as defined in iec 61993-2. 13. adjacent channel filtering is the ability of t he CMX910 filters to reject adjacent channel energy and note that it does not correspond directly to t he ?adjacent channel selectivity? as defined by iec61993-2 (or iec 62287). the filter characteristic in each of the i and q paths for 25khz mode operation is shown in figure 15. note that the pass-band has a gain of +10db and stop band is -60db so the typical rejection is +10 ? (-60) = 70db .
ais baseband processor CMX910 ? 2009 cml microsystems plc 59 d/910/6 figure 15 i/q filter response in 25khz operation. 7.1.3 operating characteristics (continued) timing diagrams figure 16 c-bus timing
ais baseband processor CMX910 ? 2009 cml microsystems plc 60 d/910/6 7.2 packaging note: the underside of the q1 package is conductive and must be electrically connected to the digital ground. the circuit board should be designed so that no unwanted short circuits can occur. figure 17 q1 mechanical outline: order as part no. CMX910q1
ais baseband processor CMX910 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of test ing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of all circuit parameters is not necessarily performed. figure 18 l9 mechanical outline: order as part no. CMX910l9

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